Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2022/239237
Kind Code:
A1
Abstract:
In the present invention, a N+ layer 3a, a first Si matrix 2 composed of a first Si matrix 2a and a second Si matrix 2b, and a N+ layer 3b are disposed in parallel with a substrate 1 and are connected with each other. A first gate insulating layer 4a surrounding the first Si matrix 2a and a second gate insulating layer 4b surrounding the second Si matrix 2b are provided. A first gate conductor layer 5a surrounding the first gate insulating layer 4a and a second gate conductor layer 5b surrounding the second gate insulating layer 4b are provided. The first gate conductor layer 5a is connected to a plate line PL and the second gate conductor layer 5b is connected to a word line 5b. The N+ layer 3a is connected to a source line and the N+ layer 3b is connected to a bit line BL. Accordingly, one dynamic flash memory cell 9 is formed. Further, a plurality of the cells are disposed in the vertical and horizontal directions with respect to the substrate 1 to form a dynamic flash memory.
Inventors:
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2021/018427
Publication Date:
November 17, 2022
Filing Date:
May 14, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
G11C16/04; G11C11/401; H01L21/8242; H01L27/10; H01L27/108
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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