Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/037446
Kind Code:
A1
Abstract:
This memory device comprises: a first impurity layer 3 and a second impurity layer 4 provided thereon in a trench which is formed in a first semiconductor layer 1 and the side walls of which are covered with a first insulating film 2; a second semiconductor layer 7 on the second impurity layer; a first semiconductor in other portions; an n+ layer 6a connected to source lines SL present at both ends of the second semiconductor layer; an n+ layer 6c connected to a bit line BL; a first gate insulating layer 8 formed on the second semiconductor layer 7; and a first gate conductor layer 9 connected to a word line WL. By controlling a voltage applied to the source lines SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL, a data retention operation for retaining a hole group, which is generated by an impact ion phenomenon in a channel region 12 of the second semiconductor layer or a gate-induced drain leak current, in the vicinity of the gate insulating layer and a data erasing operation for removing the hole group from the channel region 12 are performed.
Inventors:
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2021/033012
Publication Date:
March 16, 2023
Filing Date:
September 08, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C11/401; G11C16/04
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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