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Patent Searching and Data


Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/105604
Kind Code:
A1
Abstract:
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the page; and a page erase operation for removing the hole group from the inside of the channel semiconductor layer by controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a word line, and the second gate conductor layer is connected to a drive control line. The bit line is connected to a sense amplifier circuit. During a page read operation, page data of a memory cell group selected in at least one page is read to the bit line. A voltage of zero volts or less is applied to the drive control lines of the memory cells connected to the unselected pages among the pages during operation of the memory device.

Inventors:
SAKUI KOJI (JP)
SHIROTA RIICHIRO (TW)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2021/044837
Publication Date:
June 15, 2023
Filing Date:
December 07, 2021
Export Citation:
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Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
SHIROTA RIICHIRO (TW)
HARADA NOZOMU (JP)
International Classes:
G11C16/04; G11C11/401; H01L27/10
Foreign References:
JP2008218556A2008-09-18
JP2006080280A2006-03-23
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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