Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/281730
Kind Code:
A1
Abstract:
In this invention, a strip-shaped P-layer 2 is provided on an insulating substrate 1. Further, on both sides of the P-layer 2 in a first direction parallel to the insulating substrate, an N+ layer 3a connected to a first source line SL1, and an N+ layer 3b connected to a first bit line are provided. Furthermore, a first gate insulating layer 4a surrounding a part of the P-layer 2 connected to the N+ layer 3a and a second gate insulating layer 4b surrounding the P-layer 2 connected to the N+ layer 3b are provided. Furthermore, a first gate conductor layer 5a connected to a first plate line, and a second gate conductor layer 5b connected to a second plate line are provided, the first gate conductor layer 5a and the second gate conductor layer 5b being separate from each other and respectively covering two side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. Furthermore, a third gate conductor layer 5c connected to a first word line is provided in such a way as to surround the second gate insulating layer 4b. A dynamic flash memory is formed by the aforementioned configuration.
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Inventors:
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2021/025909
Publication Date:
January 12, 2023
Filing Date:
July 09, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
G11C16/04; G11C11/401; H01L27/10
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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