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Title:
MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE
Document Type and Number:
WIPO Patent Application WO/2012/006609
Kind Code:
A3
Abstract:
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

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Inventors:
MAHESHWARI DINESH (US)
Application Number:
PCT/US2011/043481
Publication Date:
February 23, 2012
Filing Date:
July 09, 2011
Export Citation:
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Assignee:
CYPRESS SEMICONDUCTOR CORP (US)
MAHESHWARI DINESH (US)
International Classes:
G11C7/10; G11C7/22; G11C11/413
Foreign References:
US20100103762A12010-04-29
US20080133809A12008-06-05
US20090323454A12009-12-31
Attorney, Agent or Firm:
SAKO, Bradley (LLP162 N. Wolfe Roa, Sunnyvale CA, US)
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