Title:
MEMORY-IN-PIXEL CIRCUIT, DRIVING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY APPARATUS
Document Type and Number:
WIPO Patent Application WO/2019/205485
Kind Code:
A1
Abstract:
A memory-in-pixel circuit. The memory-in-pixel circuit comprises a switch sub-circuit (102), and a data input sub-circuit (104). The data input sub-circuit (104) comprises a first floating gate transistor (Tf1) and a second floating gate transistor (Tf2). The data input sub-circuit (104) is configured to transmit a data signal from one of a plurality of data lines (106,108) to a pixel electrode (110) under control of the switch sub-circuit (102).
Inventors:
SHANG GUANGLIANG (CN)
HAN CHENGYOU (CN)
HAN MINGFU (CN)
YUAN LIJUN (CN)
YAO XING (CN)
ZHENG HAOLIANG (CN)
HAN CHENGYOU (CN)
HAN MINGFU (CN)
YUAN LIJUN (CN)
YAO XING (CN)
ZHENG HAOLIANG (CN)
Application Number:
PCT/CN2018/107961
Publication Date:
October 31, 2019
Filing Date:
September 27, 2018
Export Citation:
Assignee:
BOE TECHNOLOGY GROUP CO LTD (CN)
International Classes:
G09G3/36
Foreign References:
| KR20140099198A | 2014-08-11 | |||
| KR20140099198A | 2014-08-11 | |||
| JP2007003607A | 2007-01-11 | |||
| US20090322731A1 | 2009-12-31 | |||
| US20120038597A1 | 2012-02-16 | |||
| US20180031893A1 | 2018-02-01 | |||
| CN107025889A | 2017-08-08 | |||
| CN106935212A | 2017-07-07 |
Attorney, Agent or Firm:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS (CN)
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