Title:
MEMORY INTERFACE CIRCUIT AND MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2012/131796
Kind Code:
A1
Abstract:
A memory interface circuit (100) comprises: a voltage control unit (101) which outputs a power source voltage signal (SC1) to a power source supply unit (103); a memory I/O unit (104) which carries out transmission and receiving of data with an external memory (105); and a computation processing device (106). When timing is being corrected, the computation processing device (106) sets the power source voltage signal (SC1) such that the power source voltage supplied from the power source supply unit (103) is adjusted to a corrected voltage value, and conducts a timing correction using access data latency in each setting between the memory I/O unit (104) and the external memory (105).
Inventors:
XIAO LIMIN
Application Number:
PCT/JP2011/004947
Publication Date:
October 04, 2012
Filing Date:
September 02, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
XIAO LIMIN
XIAO LIMIN
International Classes:
G06F12/00
Foreign References:
| JP2003304150A | 2003-10-24 | |||
| JP2007133526A | 2007-05-31 | |||
| JP2010086415A | 2010-04-15 | |||
| JPH06148279A | 1994-05-27 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims: