Title:
MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM
Document Type and Number:
WIPO Patent Application WO/2008/105558
Kind Code:
A1
Abstract:
Provided is a method for managing a memory storage region used by a processor. The
processor is connected to a memory for storing data used upon execution of a task.
The storage region of the memory is divided into a plurality of blocks of different
sizes. A block of the size appropriate for the data used upon execution of the task
is selected. The data used upon execution of the task is stored in the selected
block so as to effectively arrange the data in the memory.
Inventors:
KASAHARA HIRONORI (JP)
KIMURA KEIJI (JP)
NAKANO HIROFUMI (JP)
NITO TAKUMI (JP)
MARUYAMA TAKANORI (JP)
MIURA TSUYOSHI (JP)
TAGAWA TOMOHIRO (JP)
KIMURA KEIJI (JP)
NAKANO HIROFUMI (JP)
NITO TAKUMI (JP)
MARUYAMA TAKANORI (JP)
MIURA TSUYOSHI (JP)
TAGAWA TOMOHIRO (JP)
Application Number:
PCT/JP2008/053891
Publication Date:
September 04, 2008
Filing Date:
February 27, 2008
Export Citation:
Assignee:
UNIV WASEDA (JP)
KASAHARA HIRONORI (JP)
KIMURA KEIJI (JP)
NAKANO HIROFUMI (JP)
NITO TAKUMI (JP)
MARUYAMA TAKANORI (JP)
MIURA TSUYOSHI (JP)
TAGAWA TOMOHIRO (JP)
KASAHARA HIRONORI (JP)
KIMURA KEIJI (JP)
NAKANO HIROFUMI (JP)
NITO TAKUMI (JP)
MARUYAMA TAKANORI (JP)
MIURA TSUYOSHI (JP)
TAGAWA TOMOHIRO (JP)
International Classes:
G06F9/50; G06F12/02; G06F12/06
Domestic Patent References:
| WO2005081113A2 | 2005-09-01 |
Foreign References:
| JP2003015883A | 2003-01-17 |
Other References:
YOSHIDA A.: "A Near-Fine-Grain Task Scheduling Scheme for Multi-Grain Data-Localization", IEICE TECHNICAL REPORT, vol. 96, 27 August 1996 (1996-08-27), pages 71 - 78
YOSHIDA A.: "A Data-Localization Scheme among Doall/Sequential Loops for Fortran Coarse-Grain Parallel Processing", THE TRANSACTIONS OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS D-I, vol. J-78-D-I, no. 2, 25 February 1995 (1995-02-25), pages 162 - 169
YOSHIDA A.: "A Data-Localization Scheme among Doall/Sequential Loops for Fortran Coarse-Grain Parallel Processing", THE TRANSACTIONS OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS D-I, vol. J-78-D-I, no. 2, 25 February 1995 (1995-02-25), pages 162 - 169
Attorney, Agent or Firm:
GOTO, Masaki (3-1 Kasumigaseki 3-chom, Chiyoda-ku Tokyo, JP)
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