Title:
MEMORY PERIPHERAL CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND METHOD FOR FORMING THE SAME
Document Type and Number:
WIPO Patent Application WO/2022/236946
Kind Code:
A1
Abstract:
In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes a metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.
Inventors:
SUN CHAO (CN)
CHEN LIANG (CN)
XU WENSHAN (CN)
LIU WEI (CN)
JIANG NING (CN)
XUE LEI (CN)
TIAN WU (CN)
CHEN LIANG (CN)
XU WENSHAN (CN)
LIU WEI (CN)
JIANG NING (CN)
XUE LEI (CN)
TIAN WU (CN)
Application Number:
PCT/CN2021/103755
Publication Date:
November 17, 2022
Filing Date:
June 30, 2021
Export Citation:
Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
G11C8/10; H01L27/11524; H01L29/792
Foreign References:
| US20120273862A1 | 2012-11-01 | |||
| US20100327339A1 | 2010-12-30 | |||
| CN105183379A | 2015-12-23 | |||
| CN112424933A | 2021-02-26 |
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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