MEMORY SYSTEM COMPRISING A PLURALITY OF MEMORY CONTROLLERS AND METHOD FOR SYNCHRONIZING THE SAME

Title:

MEMORY SYSTEM COMPRISING A PLURALITY OF MEMORY CONTROLLERS AND METHOD FOR SYNCHRONIZING THE SAME

Document Type and Number:

WIPO Patent Application WO2004051490

Kind Code:

A3

Abstract:

The invention relates to a memory system which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by means of operational memory commands using logical memory sector numbers. The inventive system is characterized in that for any memory operation requested by the host system (HS) the memory controller (SCx) affected with respect to a range of logical memory sector numbers (SCx) takes over the bus for communication with the host system (HS) by means of arbitration.

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Inventors:

BAUMHOF CHRISTOPH (DE)
KUEHNE REINHARD (DE)

Application Number:

PCT/EP2003/013495

Publication Date:

January 06, 2005

Filing Date:

December 01, 2003

Export Citation:

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Assignee:

HYPERSTONE AG (DE)
BAUMHOF CHRISTOPH (DE)
KUEHNE REINHARD (DE)

International Classes:

G06F12/00; G06F13/16; G06F13/18; G06F13/38; G11C7/00; (IPC1-7): G06F13/18

Foreign References:

US6026464A	2000-02-15
US6330645B1	2001-12-11
US6397314B1	2002-05-28
US5689675A	1997-11-18
US4773005A	1988-09-20

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