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Title:
MEMORY SYSTEM AND NONVOLATILE MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/095795
Kind Code:
A1
Abstract:
According to an embodiment, this memory system includes a nonvolatile memory that includes a plurality of memory cells, each of which is at least capable of storing a first bit, a second bit, and a third bit, and a memory controller that controls the nonvolatile memory. The nonvolatile memory outputs first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data pertaining to the first, second, and third bits, to the memory controller. The memory controller executes an error correction process using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.

Inventors:
AZUMA KEISUKE (JP)
HONMA MITSUAKI (JP)
ARIZONO DAISUKE (JP)
Application Number:
PCT/JP2022/043210
Publication Date:
June 01, 2023
Filing Date:
November 22, 2022
Export Citation:
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Assignee:
KIOXIA CORP (JP)
International Classes:
G06F12/00; G06F11/10; G06F12/04; G11C11/56; G11C16/26
Foreign References:
US20170046220A12017-02-16
JP2021111826A2021-08-02
US20170186484A12017-06-29
US20140237318A12014-08-21
Attorney, Agent or Firm:
SUZUYE & SUZUYE (JP)
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