Title:
MEMORY SYSTEM, MEMORY PERIPHERAL CIRCUIT, AND MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2015/198528
Kind Code:
A1
Abstract:
A memory system in which the memory blocks of a plurality of physical NAND flash memories are combined to form logical blocks, page addresses in the logical block used for writing first data larger than the physical page of the NAND flash memories are allocated so as to use the NAND flash memories successively, page addresses in the logical block used for writing second data smaller than or equal to the physical page of the NAND flash memories are allocated in order from the top of each of the NAND flash memories, and, when a merge process is performed on the first and the second data, the merge process is performed on (X-1) NAND flash memories at a maximum, X representing the number of NAND flash memories (where X is a natural number greater than or equal to 2).
Inventors:
ASO SHINGO (JP)
Application Number:
PCT/JP2015/002620
Publication Date:
December 30, 2015
Filing Date:
May 25, 2015
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
G06F12/02; G06F12/00; G06F12/06
Foreign References:
| JP2012248109A | 2012-12-13 | |||
| JP2013205872A | 2013-10-07 | |||
| JP2007193883A | 2007-08-02 | |||
| JP2012208543A | 2012-10-25 | |||
| JP2008299513A | 2008-12-11 |
Attorney, Agent or Firm:
SUGIURA, Masatomo et al. (JP)
Masatomo Sugiura (JP)
Masatomo Sugiura (JP)
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