Title:
MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2022/249528
Kind Code:
A1
Abstract:
This memory system for increasing the speed of a read operation in a memory system includes: a first pillar; a first string including a first transistor and a first memory cell; a second string including a second transistor and a second memory cell; a first bit line; a first gate lane; a first word line; a second gate line; a second word line; and a control circuit. The control circuit, when executing a read operation on the first memory cell: applies a read voltage to the first word line; applies, to the second word line, a voltage to turn off the second memory cell regardless of charge accumulated in the second memory cell; applies, to the first gate line, a voltage to turn on the first transistor; and applies, to the second gate line, a voltage to turn on the second transistor.
Inventors:
IKEGAMI KAZUTAKA (JP)
FUNATSUKI RIEKO (JP)
MOMO NOBUYUKI (JP)
SHIGA HIDEHIRO (JP)
FUNATSUKI RIEKO (JP)
MOMO NOBUYUKI (JP)
SHIGA HIDEHIRO (JP)
Application Number:
PCT/JP2022/000556
Publication Date:
December 01, 2022
Filing Date:
January 11, 2022
Export Citation:
Assignee:
KIOXIA CORP (JP)
International Classes:
G11C16/08; G11C16/04; H01L21/336; H01L27/11556; H01L27/11582; H01L29/788; H01L29/792
Foreign References:
| JP2019046529A | 2019-03-22 | |||
| JP2015228484A | 2015-12-17 | |||
| US20200411109A1 | 2020-12-31 | |||
| JP2017135238A | 2017-08-03 | |||
| US20160260732A1 | 2016-09-08 | |||
| JP2018164070A | 2018-10-18 | |||
| JP2016162466A | 2016-09-05 |
Attorney, Agent or Firm:
TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC. (JP)
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