Title:
MEMORY TRANSACTION BURST OPERATION AND MEMORY COMPONENTS SUPPORTING TEMPORALLY MULTIPLEXED ERROR CORRECTION CODING
Document Type and Number:
WIPO Patent Application WO2006057963
Kind Code:
A3
Abstract:
Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not.This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.
Inventors:
VOGT PETE (US)
Application Number:
PCT/US2005/042153
Publication Date:
July 20, 2006
Filing Date:
November 17, 2005
Export Citation:
Assignee:
INTEL CORP (US)
VOGT PETE (US)
VOGT PETE (US)
International Classes:
G06F13/28; G11C29/52
Foreign References:
| EP1313025A2 | 2003-05-21 | |||
| US5987627A | 1999-11-16 | |||
| US20020029365A1 | 2002-03-07 |
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