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Title:
MEMS CHIP WAVEGUIDE TECHNOLOGY WITH PLANAR RF TRANSMISSION LINE ACCESS
Document Type and Number:
WIPO Patent Application WO/2016/133457
Kind Code:
A1
Abstract:
The invention provides a waveguide system device realized as a MEMS chip with wafer level integrated planar RF transmission lines enabling the signal transition between the waveguide structure and the planar RF transmission line. There is also provided a micro-mechanical and/or micro-electronics(MEMS and/or IC) approach to routing of signal lines and integrating additional electrical or mechanical functions within the chip. In a second aspect the invention provides a general method of making a waveguide structure with planar RF transmission line access of the signal into the waveguide cavity structure as well as enabling on-chip electrical signal routing and integration of additional electrical or mechanical functions.

Inventors:
BAUER, Tomas (Kristinetorpsvägen 4, Bro, 197 91, SE)
Application Number:
SE2016/050233
Publication Date:
August 25, 2016
Filing Date:
March 21, 2016
Export Citation:
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Assignee:
TRXMEMS AB (Kristinetorpsvägen 4, Bro, 197 91, SE)
International Classes:
B81C1/00; B81B7/00; H01P1/208; H01P5/107; H01P7/06; H01Q13/22
Domestic Patent References:
WO2009023551A12009-02-19
WO2009023551A12009-02-19
Foreign References:
US20140368300A12014-12-18
US20100321132A12010-12-23
US20110102284A12011-05-05
US3193830A1965-07-06
US20100308925A12010-12-09
US20070229182A12007-10-04
US20140368300A12014-12-18
US20100321132A12010-12-23
US20110102284A12011-05-05
US3193830A1965-07-06
US20100308925A12010-12-09
US20070229182A12007-10-04
US20040129958A12004-07-08
Other References:
YUAN LI ET AL.: "Design and Characterization of a W-Band Micromachined Cavity Filter Including a Novel Integrated Transition From CPW Feeding Lines", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 55, no. 12, December 2007 (2007-12-01), pages 2902 - 2910, XP011196631, DOI: 10.1109/TMTT.2007.909615
UEMICHI YUSUKE ET AL.: "A ultra low-loss silica-based transformer between microstrip line and post-wall waveguide for millimeter-wave antenna-in-package applications", 2014 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS2014), 1 June 2014 (2014-06-01), TAMPA, USA, pages 1 - 3, XP032615309, DOI: 10.1109/MWSYM.2014.6848279
See also references of EP 3259229A4
YUAN LI ET AL.: "Design and Characterization of a W-Band Micromachined Cavity Filter Including a Novel Integrated Transition From CPW Feeding Lines", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 55, no. 12, December 2007 (2007-12-01), pages 2902 - 2910, XP011196631, ISSN: 0018-9480, DOI: doi:10.1109/TMTT.2007.909615
UEMICHI YUSUKE ET AL.: "A ultra low-loss silica-based transformer between microstrip line and post-wall waveguide for millimeter-wave antenna-in-package applications", 2014 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS2014, 1 June 2014 (2014-06-01), Tampa, USA, pages 1 - 3, XP032615309, ISSN: 0149-645X, DOI: doi:10.1109/MWSYM.2014.6848279
YUN LEE, DESIGN AND CHARACTERIZATION OF A W-BAND MICROMACHINED CAVITY FILTER INCLUDING A NOVEL INTEGRATED TRANSITION FROM CPW FEEDING LINES
S SONG, W-BAND BANDPASS FILTER USING MICROMACHINED AIR-CAVITY RESONATOR WITH CURRENT PROBES
M S ARIF, ALL-SILICON TECHNOLOGY FOR HIGH-Q EVANESCENT MODE CAVITY TUNEABLE RESONATORS AND FILTERS
L PELLICIA, MICROMACHINED FILTERS IN MULTILAYER TECHNOLOGY FOR ON-BOARD COMMUNICATION SYSTEMS IN KA-BAND
Attorney, Agent or Firm:
BRANN AB (P O Box 3690, Stockholm, 103 59, SE)
Download PDF:
Claims:
CLAIMS:

1. A waveguide system, comprising:

a waveguide structure comprising a waveguide (17) having at ieast one opening port (12; 74), said waveguide structure being made substantiaiiy from a silicon substrate; characterized in that

said opening port (12; 74) is structured in the wafer material above the bottom wafer; at Ieast one metal pattern (8) is provided on said silicon substrate and constitutes a signal routing and/or providing a p!anar RF transmission !ine (14), adapted to carry the signal through the opening port (12; 74) into the cavity (9; 72) of the wave-guide (17); and

a metallized probe (16; 73) provided at a distance (H) above the ground plane of the system, and coupled to said metal pattern (8, 14).

2. A waveguide system, as claimed in claim 1, with at ieast one semiconductor chip (RFIC) assembled onto and electrically connected to the metal pattern (8)

constituting signal routing and / or a planar RF transmission line (14).

3. A waveguide system, as claimed in claim 1, with at ieast one antenna port (6), structured in the top wafer substrate, opening into the waveguide cavity structure.

4. A waveguide system, as claimed in claim 1 , with at Ieast one passive component, selected from a capacitor, varactor, resistor, pin diode or fieid effect transistor, assembled and electrically connected to the waveguide system.

5. A waveguide system, as claimed in claim 1 , with at Ieast one passive component selected from a capacitor, resistor, varactor, pin diode or fieid effect transistor, assembled and electrically connected to the metal pattern constituting signal routing and planar RF transmission line (14).

6. A waveguide system, as claimed in claim 1 , with at least one wafer level integrated mechanical tuning element (26) inside the waveguide.

7. A waveguide system, as claimed in claim 1, with at least one wafer level integrated ridge (24) inside the waveguide.

8. A waveguide system, as claimed in claim 1 , with at least one wafer level integrated "iris" (25) inside a waveguide.

9. A waveguide system, as claimed in claim 1 , with at ieast one wafer level integrated tuning element (26) inside the waveguide.

10. A waveguide system, as claimed in claim 1 , with at least one through substrate via (TSV) connecting a metal pattern constituting signal routing and planar RF transmission iine to an isoiated contact pad at the top or bottom surface of the waveguide system.

11. A waveguide system, as claimed in claim 1 , with at least one wafer !evei integrated electrostatically actuated mechanical feature connected to the metal pattern constituting signal routing and planar RF transmission Sine.

12. A waveguide system, as claimed in claim 1 , with at least one wafer level integrated piezoelectricaily actuated mechanical feature connected to the metal pattern constituting signal routing and planar RF transmission line.

13. A waveguide system, as claimed in claim 1 , with at least one wafer level integrated passive electric function realized in the metal pattern constituting signal routing and planar RF transmission Sine.

14. A waveguide system, as cSaimed in ciaim 1 , wafer ieveS integrated with a semiconductor device.

15. A waveguide system, as claimed in cSaim 1 , where at least one of the cavity structures is filled with a dielectric material other than air, to modify the RF properties of the cavity.

16. A waveguide system as claimed in ciaim 1 , wherein the waveguide system comprises at least one, preferably a plurality of slot antennas (27). provided in the top wafer structure (3).

17. The waveguide system as claimed in claim 16, wherein the slot antennas (27), comprise slots (27).

18. The waveguide system as claimed in claim 17. wherein the length L of the slots (27) is L - (λ/2 + n λ) + 20%, preferably + 10%, wherein λ is the wave length of the working frequency of the device and n = 0. 1 , 2, , and the width is suitably essentially λ/3 to λ/15, preferably about λ/10.

19. The waveguide system as claimed in claim 16, 17 or 18, wherein there are provided a plurality of cavities (28, 28') provided with at least one slot (27) in at least one cavity (28, 28').

20. A method of manufacturing a MEMS based waveguide system with wafer level integrated planar RF transmission lines comprising the following steps:

providing at least two starting substrates in the form of semiconductor wafers, preferably silicon wafers, glass wafers or SO! wafers, having two sides;

processing at least one wafer from at least one side to achieve a plurality of high aspect ratio vertical features by means of a sequence of standard substrate lithography patterning and subsequent substrate etching steps such as, but not limited to, Deep Reactive !on Etching (DR!E) where some features may constitute holes extending through the entire thickness of the wafer;

depositing metai on at least two wafers in the wafer stack by means of a wafer level process such as sputtering, e!ectroplating, evaporation or screen printing on at least one side of each wafer;

positioning at least two of the wafers in the stack with the metal coated surfaces facing each other where at least one of the metallized surfaces has been patterned with a planar RF transmission Sine.

optionally, in the case of realizing the metal pattern on top of a conducting or semiconducting substrate, providing

i) an isolation layer in the shape of a residua! buried oxide from an SOI starting substrate or

ii) creating an isolation layer on the top surface underneath the patterned metal; joining two wafer substrates with metal surfaces facing each other through a sequence of MEMS wafer bonding steps, including optionally wafer etching, thinning and back-grinding and also metallization to form the wafer bonding interfaces for MEMS wafer bonding; and

separating the individual MEMS chips containing the waveguide system.

21. The method according to claim 19, wherein separating the chips includes etching, dicing, stealth dicing, cleaving or laser dicing the substrate wafer stack into individual chips.

Description:
MEMS CHIP WAVEGUIDE TECHNOLOGY WITH PLANAR RF TRANSMISSION LINE ACCESS

The invention discioses a waveguide MEMS chip technology enabling wafer level integrated planar RF transmission line access into the waveguide structure. The waveguide technology with wafer level integration of signal access enables a plurality of smart high frequency functions realized as MEMS microchips with facilitated possible on-chip integration of radio frequency integrated circuits (RFIC) and other functionalities. A wafer ieve! method of making the waveguide structure with signal access is disclosed, where the completed MEMS chip is comprised of at least two wafer substrates that are bonded together using wafer bonding technology.

DESCRIPTION

The present invention relates to a waveguide structure realized as a chip built in MEMS technology incorporating a novel functionality with respect to signal transition into the waveguide and possible on-chip integration of Radio Frequency integrated circuits.

BACKGROUND OF THE INVENTION

Mainstream waveguide technology requires costly high precision machining of metal parts that very often fall short of achieving required RF specification directly in the machining process and hence require additional costly tuning of the waveguide parts to achieve the desired performance.

Wireless telecommunication is continuously looking to expand into higher frequency bands for wireless communication, and as high frequency means shorter wavelength, this also implies that waveguide systems need to be realized with smaller feature size. MEMS wafer processing technology inherently holds the key capability of enabling very precise and repeatabie micromachining of micro scale

electromechanical systems in mass production, in future transceiver systems it is of interest to achieve very small and precise waveguide structures using micro manufacturing technologies with inherent high precision and repeatability in high volume manufacturing, thus enabling the possibility of making low cost mechanical waveguide structures that meet specifications for the intended RF frequency without need for additional tuning. Furthermore, a cost efficient method of coupling the signal into the cavity filter is desirable as well as possibly integrating also the radio frequency integrated circuit (RFiC) with high precision relative to the waveguide structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1-6 shows the MEMS based waveguide system technology exemplified as a waveguide cavity filter with planar RF transmission line signal access into the cavity filter structure and on-chip integration of radio frequency integrated circuits.

DETAILED DESCRIPTION OF THE INVENTION The present invention discloses the inventive concept of a waveguide cavity structure formed out of at least two structured and metallized wafer substrates bonded together and having a planar RF transmission line signal routing access to the waveguide cavity structure reaiized using the metaiiization iayer deposited on the wafer substrate materia! of at !east one of the wafers in the wafer stack.

Such cavity waveguide structure, having impedance adapted RF signal access, enables a plurality of applications, e.g. microwave waveguide cavity filters, antenna systems, straight waveguides and orthomode transducers OMT. The resulting highly integrated waveguide chip is suitable for deployment in high frequency transceiver (TRX) systems in general.

The invention can be used to make a single radio communication chip integrating for example the microwave cavity filter, antenna port, antenna and radio frequency integrated circuits (RFIC) into one single microsystem, in such realization, the microwave waveguide cavity filter on the transmitter side filters out the selected signal frequency and passes it on to the antenna. On the receiver side it filters out the desired RF signal and feeds it into the receiving chip. With the migration to higher frequencies and shorter wavelength, the invention also holds a broader deployment area as a semiconductor manufacturing based mass production platform for highly integrated high frequency broadband communication solutions (waveguide tnterposers) based on the disclosed micro scale waveguide MEMS chip technology.

FIG. 1 shows a singulated (diced) MEMS chip. 1, 2 and 3 show the residual wafer bonding interfaces from the integration of multiple structured wafers assembled on top of each other in a wafer stack that constitutes the waveguide chip technology. The MEMS chip is suitably made of structured silicon or glass wafers bonded together, although other materials are possible. 4 and 5 represents optional RFiC's mounted directly on the MEMS chip. 6 represents an optional antenna port structured in the top wafer substrate.

FiG 2. shows in more detail how an RFIC can be integrated by means of 7 wire bonding technology (or flip chip technology) to connect the RFIC to a pattern of metal traces 8 on the top surface of a wafer. The metal traces 8 defined on the surface of a wafer in the wafer stack has the function to constitute pads for wire bonding interconnects as well as routing electrical signals to a select position on the chip and finally also constituting the planar RF transmission line signal access into the cavity structure 9. The wafer level patterned metal traces 8 constitutes both a separate signal routing and a planar RF transmission line. Another functional feature of the metal traces can be the provision of a wafer level integrated capacitor structures.

FiG 3. shows how electrical access can be realized from wire bond pads 10 at the edge of the MEMS waveguide chip, carrying multiple electrical connections to an on- chip mounted RFIC 11 eventually connecting to a planar RF transmission line carrying the signal through an opening port 12 in the waveguide, structured in the wafer material above the bottom wafer, and of varying height and width to

accommodate required RF impedance matching.

FIG 4. 13 shows the bottom of the MEMS chip that may have an optional metal coating to facilitate heat distribution and dissipation and also constitute an RF shield or ground plane for the pianar RF transmission line structures (copianar or

microstrip).

FiG 5. shows an embodiment of the pianar RF transmission !ine signai access defined in the patterned meta! on one of the wafers' top surface by means of separating the signal trace 14 from the systems ground plane using an isolating gap 15 in the metal pattern. A metallized "probe" 16 is structured in the wafer material protruding from the ground plane of the system, allowing the resulting structure to act as an antenna inside the waveguide cavity, thereby allowing an efficient transition of the signal between the pianar RF transmission line and the waveguide 17. In the case of realizing the metal pattern on top of a conducting or semiconducting substrate, an isolation iayer must be present in the shape of a residua! buried oxide from an SOI wafer or be created on the surface underneath the patterned metal. In the same substrate planes that support the metal trace pattern, other protruding metallized or non-metallized protruding elements of the waveguide structure can be realized such as additional waveguide access ports and openings, tuning elements 18, waveguide cavity "ridges" 19 as well as the side wails and "irises" 20 of the waveguide cavity structure.

FiG 6. shows an exploded view of the MEMS waveguide chip looking from the bottom into the top of a structured wafer 21 where 21 constitutes a functional match to 22. Most of the 21 wafer surface facing 22 is metallized to contain the RF signal inside the cavity circumference but may also have the metal Iayer patterned and may also contain additional features such as waveguide antenna port structures 23, "ridges" 24, "irises" 25 and "tuning elements" 26. 21 and 22 aligned and snapped together in the same horizontal plane constitute the completed waveguide chip solution as in FIG 1.

In Fig. 7 another embodiment of the invention is disciosed. The waveguide 70 is only schematically indicated.

Here there is no protruding "probe" extending from the ground plane of the system. Instead a spacer element is provided in form of a silicon ridge or rim 71 that has a finite height H over the ground piane of the system, i.e. the bottom of the waveguide cavity 72. This ridge or rim is metallized 73 and extends from outside of the cavity through the opening 74 in the side wall 76 of the cavity 72. The metallization that is provided at a distance above the ground plane and will have the same function as the probe 16 disclosed in Fig. 5.

In a preferred embodiment the waveguide system comprises at least one, preferably a plurality of slot antennas, provided in the top wafer structure 3. This is shown schematically in Fig. 8.

Thus, in the top wafer 3 a plurality of narrow slots 27 are provided (not to scale in the figure). The siots open into a cavity or several cavities schematically indicated with a broken line contour 28.

The slots 27 are typically and preferably half a wave length (λ/2) long and a tenth of a wavelength wide, and are preferably laid out in a pattern as shown, where every second slot is on one side of the middle M of the extension of the wave guide and every second on the other said i.e. in a "staggered" configuration, although this is not strictly necessary. The slots are suitably spaced apart about half a wave length in longitudinal direction (shown with arrow L). Preferably the slots are located

essentially at equal distances from an imaginary center line indicated with M in Fig. 7, and the outer contour of the waveguide cavity 28, i.e. they are suitably arranged on a line indicated with C1 and C2. respectively, in Fig. 7.

In embodiments there can be provided several arrays of slots 27 in adjacent cavities 28, 28' as shown in Fig. 8. The number of cavities is not limited by other than practical considerations, and there should preferably be at least one slot in each cavity, although it would be possible to have some cavities without slots.

The length L of the slots could in principle be approximately {+ 10% to + 20%) given as L = (λ/2 + ηλ), wherein n = 0, 1 , 2, , and λ is the wave length of the working frequency of the device, but the performance would not be as good for n > 0. The width of the slots is suitably essentially λ /3 to λ /15, preferably about λ /10.

In one method of making the waveguide system, at least two starting substrates in the form of a semiconductor wafer, preferably but not limited to an SOI wafer (Silicon On Insulator), high resistivity silicon wafer or glass wafer is provided, having two sides. At least one wafer is processed to achieve a plurality of high aspect ratio vertical features on at least one side of the wafer by means of a sequence of standard substrate lithography patterning and subsequent substrate etching steps such as Deep Reactive Ion Etching (DRIE), where some features may constitute hole features extending through the entire thickness of the wafer.

At least two wafers in the wafer stack have metal deposited by means of a wafer level process such as sputtering, electroplating, evaporation, spray painting or screen printing on at least one side of the wafer and the metallized surfaces of at least two of the wafers in the stack are facing each other where at least one of the metallized surfaces has been patterned to constitute a planar RF transmission line as in FiG. 5 14. In the case of realizing the metal pattern on top of a conducting or

semiconducting substrate surface, an isolation layer must be present in the shape of a residual buried oxide from an SOI wafer or be created on the top surface

underneath the patterned metal.

The processed wafer substrates are joined together in a sequence of MEMS wafer bonding steps that may contain optional wafer etching, thinning and backgrinding steps and also metallization steps to form the wafer bonding interfaces for MEMS wafer bonding. An etching or dicing step separates the individual MEMS chips from the bonded wafer structure and RF iC's can optionally be mounted on the MEMS chip by a suitable die attach technology (like wire bonding, gluing or flip chip bonding) directly on the patterned metal layer as represented in FIG. 1.