Title:
MEMS DISPLAY PIXEL CONTROL CIRCUITS AND METHODS
Document Type and Number:
WIPO Patent Application WO/2012/166941
Kind Code:
A3
Abstract:
This disclosure provides latching circuits, and pixel circuits and display devices that include such latching circuits. The latches herein include a switch positioned on an interconnect which couples two crosscoupled inverters of the latch. The switch is configured to control a passage of a current between the first and second inverters. By switching the switch OFF at a time a data voltage is transferred to the inverters, any leak current between the inverters can be interrupted. As a result, a malfunctioning of the data latch is prevented.
Inventors:
MIYAMOTO MITSUHIDE (JP)
MATSUMOTO KATSUMI (JP)
KURANAGA TAKAHIDE (JP)
MATSUMOTO KATSUMI (JP)
KURANAGA TAKAHIDE (JP)
Application Number:
PCT/US2012/040238
Publication Date:
February 21, 2013
Filing Date:
May 31, 2012
Export Citation:
Assignee:
PIXTRONIX INC (US)
JAPAN DISPLAY EAST INC (JP)
MIYAMOTO MITSUHIDE (JP)
MATSUMOTO KATSUMI (JP)
KURANAGA TAKAHIDE (JP)
JAPAN DISPLAY EAST INC (JP)
MIYAMOTO MITSUHIDE (JP)
MATSUMOTO KATSUMI (JP)
KURANAGA TAKAHIDE (JP)
International Classes:
G02B26/08; G09G3/34; G11C11/412
Foreign References:
| US20020051096A1 | 2002-05-02 |
Other References:
See also references of EP 2715940A2
Attorney, Agent or Firm:
GORDON, Edward A. (111 Huntington Ave.Boston, Massachusetts, US)
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