CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application Serial No.

62/561 ,947 entitled " MEMS MICROPHONE SYSTEM " by Herms et al., filed

September 22, 2017, the disclosure of which is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

[0002] The disclosure is directed toward microelectromechanical systems (MEMS) and, in particular, to MEMS microphones.

BACKGROUND

[0003] Previously known MEMS microphone chip designs included a fixed electrode formed by a thick, perforated epipoly layer, below which was a patterned polysilicon membrane with anchor structures and springs attached via oxide spacers. In order to fabricate such chips, the polysilicon and sacrificial oxide layers are deposited and then the latter are etched away by gas phase etching. Thus the membrane is released and free to move. However, the fabrication process resulted in the front side of the membrane being opened and susceptible to particle and moisture contamination.

[0004] Newer MEMS chips have been designed to be less susceptible to particle contamination. For example, a Pancake design (based on the "Steel City" approach) as been developed which uses two completely closed, flexible, mechanically coupled membranes with a polysilicon electrode in between. The displacement of the membrane due to sound pressure leads to capacity changes within the inner electrodes, which in turn can be read out from the ASIC.

[0005] The fabrication process for MEMS chips, according to the pancake approach, have typically required wet chemical etching processes to release the membranes. It is critical that the MEMS chip then go through a stiction-free drying process. Such drying processes can be complex and elaborate.

[0006] What is needed is a method of fabricating a particle-immune MEMS

microphone chip that does not require wet chemical etching and that has additional advantages known MEMS microphone designs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a schematic cross-sectional view of a wafer after a first oxide layer has been deposited thereon and patterned in a process of fabricating a MEMS microphone.

[0008] FIG. 2 is a schematic cross-sectional view of the wafer of FIG. 1 after a first

SiCN membrane layer has been deposited onto the first oxide layer.

[0009] FIG. 3 is a schematic cross-sectional view of the wafer of FIG. 2 after a first polysilicon layer has been deposited onto the first SiCN layer and patterned to form first electrodes.

[0010] FIG. 4 is a schematic cross-sectional view of the wafer of FIG. 3 after a second oxide layer has been deposited thereon and polished.

[0011] FIG. 5 is a schematic cross-sectional view of the wafer of FIG. 4 after a third oxide layer has been deposited thereon. [0012] FIG. 6 is a schematic cross-sectional view of the wafer of FIG. 5 after a second polysilicon layer has been deposited thereon and patterned to form second electrodes.

[0013] FIG. 7 is a schematic cross-sectional view of the wafer of FIG. 6 after a fourth oxide layer has been deposited thereon and polished.

[0014] FIG. 8 is a schematic cross-sectional view of the wafer of FIG. 7 after trenches are formed down to the first SiCN layer.

[0015] FIG. 9 is a schematic cross-sectional view of the wafer of FIG. 8 after a second SiCN layer has been deposited on the fourth oxide layer and on the walls of the trenches.

[0016] FIG. 10 is a schematic cross-sectional view of the wafer of FIG. 9 after a fitth oxide layer has been deposited thereon.

[0017] FIG. 1 1 is a schematic cross-sectional view of the wafer of FIG. 10 after a polishing step.

[0018] FIG. 12 is a schematic cross-sectional view of the wafer of FIG. 1 1 after a third SiCN layer has been deposited thereon and after a third polysilicon layer has been deposited thereon and patterned to form third electrodes.

[0019] FIG. 13 is a schematic cross-sectional view of the wafer of FIG. 12 after perforating the second and third SiCN layers.

[0020] FIG. 14 is a schematic cross-sectional view of the wafer of FIG. 13 after a sixth oxide layer has been deposited thereon and polished.

[0021] FIG. 15 is a schematic cross-sectional view of the wafer of FIG. 14 after a seventh oxide layer has been deposited thereon. [0022] FIG. 16 is a schematic cross-sectional view of the wafer of FIG. 15 after a fourth polysilicon layer has been deposited thereon and patterned to form fourth electrodes.

[0023] FIG. 17 is a schematic cross-sectional view of the wafer of FIG. 16 after a seventh oxide layer has been deposited thereon and trenches have been formed that extend down to the third SiCN layer.

[0024] FIG. 18 is a schematic cross-sectional view of the wafer of FIG. 17 after a fourth SiCN layer has been deposited thereon.

[0025] FIG. 19 is a schematic cross-sectional view of the wafer of FIG. 18 after an eighth oxide layer has been deposited thereon and polished.

[0026] FIG. 20 is a schematic cross-sectional view of the wafer of FIG. 19 after a fifth SiCN layer has been deposited thereon and perforated and after a protective layer has been deposited on top of the fifth SiCN.

[0027] FIG. 21 is a schematic cross-sectional view of the wafer of FIG. 20 after the wafer has been flipped over.

[0028] FIG. 22 is a schematic cross-sectional view of the wafer of FIG. 21 after a backside etching step.

[0029] FIG. 23 is a schematic cross-sectional view of the wafer of FIG. 22 after an oxide etching step.

[0030] FIG. 24 is a schematic cross-sectional view of the wafer of FIG. 23 after depositing a nitride layer under low pressure to close the etch access holes DETAILED DESCRIPTION

[0031] For the purposes of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiments illustrated in the drawings and described in the following written specification. It is understood that no limitation to the scope of the disclosure is thereby intended. It is further understood that the present disclosure includes any alterations and modifications to the illustrated embodiments and includes further applications of the principles of the disclosure as would normally occur to a person of ordinary skill in the art to which this disclosure pertains.

[0032] The present disclosure is directed to a particle-immune MEMS microphone using a thin film approach and that uses silicon carbonitride (SiCN) material as membrane material. As an alternative to SiCN, silicon rich nitride (SiRiN) is also considered. As discussed below, the MEMS sensor includes a cavity which is enclosed by an "upper" and "lower" membrane and corresponding side walls. The cavity encapsulates the electrodes used for capacitive sensing in a vacuum. Encapsulating the electrodes in a vacuum between the closed membranes provides particle immunity and moisture insensitivity.

[0033] The electrodes are formed of a conductive material, such as polysilicon, and are supported on the upper and lower membranes which are formed of SiCN (or, alternatively, SiRiN). SiCN offers advantageous properties for MEMS microphones. SiCN is dense and resistant to HF acid etching which is the primary etchant used for oxides. Therefore, SiCN has high etching selectivity with regard to silicon oxide for end point detection. SiCN also has a tensile stress in the range of 100 Mpa - 400 Mpa which fits well with the requirements of a MEMS-based microphone (estimated target value approx. 100-200 MPa tensile stress). The electrical layer resistance of SiCN has been measured in the range of 1019 Ω/sq at room temperature under a dry atmosphere. This high value is helpful when the mechanical components of a MEMS microphone are to be decoupled from the electrical functions.

[0034] A thin film-based MEMS microphone 10 using SiCN as membrane material will now be described with reference to FIGS.1 -24. All the oxide and nitride layers discussed below are deposited to a thickness of approximately 250 nm - 500 nm. The process begins with the deposition and patterning of a first oxide layer 14 on a substrate or wafer 12 as depicted in FIG. 1 . A first SiCN layer 16 is then deposited onto the first oxide layer 14 to serve as a lower flexible membrane for the device 10 (FIG. 2).

[0035] A first polysilicon layer 18 is deposited onto the first SiCN layer 16 and patterned to form a first electrode on the lower membrane (FIG. 3). A second oxide layer 20 is then deposited onto the first oxide layer 14 and the first electrode 18. The second oxide layer 20 is polished to remove the oxide sitting on top of the first electrode 18 as can be seen in FIG. 4.

[0036] Referring to FIG. 5, a third oxide layer 22 is deposited onto the second oxide layer 20. A second polysilicon layer 24 is then deposited onto the third oxide layer 22 and is patterned to form a second electrode (FIG. 6). A fourth oxide layer 26 is then deposited onto the third oxide layer 22 and the second electrode 24 which is polished to remove the portions of the oxide on the second electrode 24 (FIG. 7). The second electrode 24 is a counter electrode for the electrode 18 such that the first electrode 18 and second electrode 24 form a first capacitive sensor. The second oxide layer 22 in the regions between the electrodes 18, 24 and between the trenches 28 is a gap oxide for first capacitive sensor.

[0037] As depicted in FIG. 8, a patterning step is conducted to form a plurality of trenches 28 that extend through the oxide layers 20, 22, 26 down to the first SiCN layer 16. Referring now to FIG. 9, a second SiCN layer 30 is then deposited onto the fourth oxide layer 26. The second SiCN layer 30 is also deposited into the trenches 28 and lines the walls of the trenches 28 as can be seen in FIG. 9. The second SiCN layer 30 will support the second electrode 24 once the gap oxide has been removed to form a gap between the electrodes 18, 24.

[0038] Referring now to FIG. 10, a fifth oxide layer 32 is deposited onto the second SiCN layer 30 to fill the trenches 28. The fifth oxide layer 32 is then polished so that only the oxide in the trenches 28 remains (FIG. 1 1 ). A third SiCN layer 34 is then deposited onto the second SiCN layer 30 and over the oxide filled trenches 28 (FIG. 12). A third polysilicon layer 36 is then deposited onto the third SiCN layer 34 and patterned to form a third electrode (FIG. 12). A patterning step is also conducted to form perforations 38 that extend through the second SiCN 30 and third SiCN 34 layers down to the fourth oxide layer 26.

[0039] Referring now to FIG. 14, a sixth oxide layer 40 is deposited onto the third SiCN layer 34 and the third electrode 36. As can be seen in FIG. 14, the sixth oxide layer 40 is polished to remove the portions of the oxide on the third electrode 36.

Referring to FIG. 15, a seventh oxide layer 42 is then deposited onto the polished sixth oxide layer 40 and the third electrode 36 (FIG. 15). [0040] A fourth polysilicon layer 44 is then deposited onto the seventh oxide layer and patterned to form a fourth electrode (FIG. 16). The second and third SICN layers 30, 34 form an intermediate membrane which is part of the counter electrode assembly. The third electrode 36 is supported on the third SiCN layer and is a counter electrode for the fourth electrode 44 such that the third electrode 36 and fourth electrode 44 form a second capacitive sensor. The seventh oxide layer 42 in the regions between the electrodes 36, 44 and between the trenches 28 is a gap oxide for second capacitive sensor.

[0041] Referring to FIG. 17, an eighth oxide layer 46 is deposited onto the seventh oxide layer 42 and the fourth electrode 44 and then polished. A patterning step is then conducted to form a plurality of trenches 48 that extend down to the third SiCN layer 34. The trenches 48 above the third SiCN layer 34 will be referred to herein as upper trenches, and the trenches 28 located between the first and second SiCN layers will be referred to herein as lower trenches. As can be seen in FIG. 17, each of the upper trenches 48 is aligned with a lower trench 28.

[0042] A fourth SiCN layer 50 is then deposited onto the eighth oxide layer 46 and the fourth electrode 44 (FIG. 18). The fourth SiCN layer 50 is also deposited into the upper trenches 48 to line the walls of the trenches as can be seen in FIG. 18. A ninth oxide layer 52 is deposited onto the fourth SiCN layer 50 so as to fill the upper trenches 48 and polished so that only the oxide in the trenches remains.

[0043] Referring to FIG. 20, a fifth SiCN layer 54 is then deposited onto the fourth SiCN layer 50 and over the oxide filled upper trenches 52. The fourth and fifth SiCN layers form an upper membrane for the device. A patterning step is also conducted to form perforations 56 that extend through the fourth SiCN and fifth SiCN layers 50, 54 down to the eighth oxide layer 46. These perforations 56 will serve as etch access holes for etching the interior oxide in a later step. A thick oxide protection layer 58 is formed on the fifth SiCN layer 54 to protect the upper layers so that the wafer may be flipped over as can be seen in FIG. 21 .

[0044] Once the device 10 has been flipped over, a backside etching process is performed which removes the portion of the wafer 12 below the active region to release the underside of the lower membrane 16 (FIG. 22). Referring now to FIG. 23, the device 10 is then flipped back over so that oxide etching may be performed to remove oxides including the gap oxide layers and other oxide layers from within the cavity 64. The etchant is introduced via the etch oxide holes 38, 56 in the SiCN layers 50, 54 using a gas phase etching process.

[0045] Referring to FIG. 24, a nitride protection layer 60 is then deposited over the fifth SiCN layer 54 under lower pressure, e.g., 1 .3 mbar or less, to seal the etch access holes 56. This results in the cavity being sealed with a low pressure atmosphere that is also 1 .3 mbar or less. .

[0046] As can be seen in FIGS. 23 and 24, the removal of the oxide from between the center-most oxide filled trenches forms a channel 62 that extends though the upper and lower membranes. This channel 62 serves as a leak hole for barometric pressure equalization and for controlling the frequency behavior of the device.

[0047] The upper membrane (SiCN layers 50, 54) and lower membrane (SiCN layer 16) close both sides of the device thereby encapsulating the cavity 64 in which the capacitor electrodes 18, 24, 36, 44 are located. Since the lower membrane and the upper membrane are substantially nonporous, at least with respect to dust particles and moisture, the device is particle immune and moisture insensitive. The oxide filled trenches 28, 48 are aligned to form pillars within the cavity which maintain spacing between the membranes. The pillars in conjunction with the use of SiCN support layers enable wider device geometries.

[0048] Please note that the process depicted and described with reference to FIGS. 1 -24 should not be considered as limiting to the overall process. Additional steps or few steps may be used. Additional layer deposition and patterning steps may be included for various reasons, such as readout circuitry, other device fabrication and the like.

[0049] As noted above, all the oxide and nitride layers are deposited to a thickness of approximately 250 nm - 500 nm. The SiCN may be deposited using a chemical vapor deposition process such as plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). The oxide may be deposited in any suitable manner. The SiCN may be structured using a gas phase etching process with a sulfur hexafluoride (SF6) based etching material. The structuring of the oxide layers can also be carried out using HF etching, as well as plasma or wet chemical etching processes, depending on the manufacturing tolerances provided in the design.

[0050] SiRiN may be used as an alternative to SiCN in the process described in FIGS. 1 -24. The primary difference between the use of SiCN as described above and the use of SiRiN for the membrane layers is that the release of the membrane with the backside etching process would likely have to be carried out by wet chemical etching rather than gas phase etching. If wet chemical etching is used, a stiction-free drying process must be used to dry the device. [0051] The thin film approach using SiCN membranes for MEMS microphones described above provides a number of advantages over previously known devices and processes. For example, the HF resistance of the SiCN material allows the membrane to be released using a state-of-the-art gas phase etching process. A wet etching release process with a very elaborate, stiction-free drying process requirement is omitted.

[0052] Compared to the polysilicon membranes in current microphone processes, electrical functions are decoupled from the mechanical membrane. As a result, electrical supply lines become smaller, which reduces the combined electrical parasitic

impedance. Moreover, by decoupling the electrode and the mechanical membrane, a simple realization of multiple electrodes per membrane is obtained, which allows for extended functionalities (different sensitivity ranges for high-SPL, possibly pressure sensor functions, etc.).

[0053] Wafer processing in previously known particle-immune microphone fabrication processes typically require about 35 mask planes. The process described above requires about 16 mask planes so the process i may be performed with less complexity than previously known processes. Compared to other particle-immune microphone designs (e.g., "Steel City - Pancake" approach), the tensile strength of SiCN layers can be used to reduce the induced stress-gradient asymmetries in the evaluation capacities. The use of SiCN also enables a reduction of mechanical asymmetries within the MEMS by using tensile (SiCN) rather than compressive materials and avoiding high- temperature epitaxy processes.

[0054] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, the same should be considered as illustrative and not restrictive in character. It is understood that only the preferred embodiments have been presented and that all changes, modifications and further applications that come within the spirit of the disclosure are desired to be protected.