The present invention relates generally to message communication and more particularly describes novel apparatus and techniques for reliably conveying messages to individuals or groups of individuals.

It is often desirable to reach individuals without disturbing them when a transmitted message is received, while also allowing such individuals to view the message at their convenience.

Heretofore, paging systems have generally been designed to reach a selected person who is made aware of the page by a beeper sound or the like upon which the paged person goes to the nearest telephone and calls the originator of the paging signal for the message.

Another type of paging system has the ability to receive the message, providing the recipient with a paging signal followed by a voice message. A person carrying a paging system of either ^' type -may not wish to be disturbed, such as an attorney during court proceedings, and such person will turn off the paging device which loses the ability to inform the person that a message is intended for him. A person using the second type of paging system may be unable to understand the voice message in a noisy envir- onment or unable to make notes of the voice message such as when operating a motor vehicle. If the person desires to review the voice message, he must telephone the originator of the message.

With another type of prior art system, the person is provided with a paging system that has the ability to receive the message and retain it as hard copy. Such a system is described in U. S. Letters Patent No. 3,846,783 which issued on November 5, 1974. However, even that system lacked the ability to store messages in digitally encoded form so that the message

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may be reproduced whenever the recipient desires. Said system' also lacked the ability to: provide each receiver with a plurality of addresses , remotely add or delete addresses from the personal receiver, and predetermine the character count of the transmitted message avoiding the possibility of a lost end of message character in transmission.

Accordingly, it is an important object of the present invention to provide a personal receiver that is light, compact and reliable enough to be carried by individuals.

It is a further object of the present invention to provide a first address uniquely identifying each receiver. It is a further object of the present invention to provide a further address identifying a common group of receivers.

It is yet a further object of the present invention to have the capability to remotely add or delete or modify an address of the receiver.

It is still a further object of the present invention to store the message until the recipient is able to conveniently view the message on a visual display.

It is yet another further object of the present invention to allow the recipient to selectively view, retain, or delete messages stored in the personal receiver.

It is a further object of the present invention to warn the recipient when the receiver is out of range of the transmitting antenna.

It is a further object of the present invention to combine sequentially repeated transmission of the same message while storing the maximum number of error free characters of the single message.

SUMMARY OF THE PRESENT INVENTION

According to the invention, a binary encoded data train is developed and transmitted, where the data train has a message portion and a header preceding the message portion. The header signals include a plurality of synch signals, a first control signal marking the end of the synch signals, at least a first address signal, the first control signal also marking the beginning of each address signal in the event the header includes a plurality of address signals, a second control signal to mark the end of all address signals, and a message length signal which contains information of the total character count of the message portion.

A personal receiver includes synch means for preparing the personal receiver for reception of the data train and an address means responsive to the address signal. The address means includes a first addressable means responsive.to an address signal uniquely identify¬ ing the personal receiver and a second addressable means programmable by the message portion. In an ad¬ dressed personal receiver, a message means receives and stores the message portion and selectively displays the message portion in alphanumeric characters.

Numerous other features, objects and advantages of the present invention will become apparent from the following specification when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a block diagram illustrating the transmitting system and the personal receiver;

FIGURE 2a shows a formatting diagram of the header and message portions developed by the transmitting system of FIGURE 1;

FIGURE 2b shows a stacked and repeated data train format;

FIGURE 2c shows a format of a further sequen¬ tially transmitted data train utilized by the personal receiver;

FIGURE 3 is a more detailed schematic block diagram illustrating the receiver/demodulator of FIGURE 1;

FIGURE- 4 is a more detailed schematic block diagram illustrating the bit synchronizer of FIGURE 1; FIGURE 5 is a more detailed schematic block diagram illustrating the decoder of FIGURE 1;

FIGURE 6 is a flow diagram of the program and operation of the decoder in the receiver shown of FIGURE 5 illustrating the initialization routine; FIGURE 7 is a flow diagram of the program and operation of the decoder in the receiver shown in FIGURE 5 illustrating the executive routine;

FIGURE 8 is a flow diagram of the program and operation of the-decoder of the receiver shown in FIGURE 5 illus ^' trating the interrupt service routine.

DETAILED DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a schematic block diagram illustrating the overall message communication system comprising transmitting means 10 and a personal receiver 11. The system illustrates the manner in which a message entered at a visual message source 12 is viewed on a visual alphanumeric display 13 built into personal receiver 11 carried by the intended recipient or plural¬ ity of recipients. Visual message source 12 encodes the message into a series of binary logic levels or data bits and applies the message in the digitally encoded form to a visual message processor 14, which then converts the digital data into a corresponding sequence of audio frequencies for modulating transmitter 15, preferably by

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frequency modulation, to radiate a ^' binary encoded data train from an antenna 16.

A receiving antenna 17 receives the transmitted energy and applies it to a receiver/demodulator 18 which includes the usual circuits for detecting the binary encoded data train and demodulating the carrier modulated by the audio frequencies into the corresponding sequence of binary logic levels. The demodulated digital data is then applied to a bit synchronizer 19 which synchro- nizes the internal clocks of personal receiver 11 to the incoming data train so that each of the binary data bits can be properly sampled and applied to a decoder 20 which stores the message prior to display of said message on visual alphanumeric display 13. Visual message source 12 may be a standard keyboard terminal* such as -the Lear Siegler Inc. , Model ADM-3A Dumb Terminal which converts alphanumeric char¬ acters to binary encoded electrical signals such as the ASCII code which..is well known in the art. Each char- acter of the ASCII code contains one start bit, seven information bits, one parity bit, and two stop bits. Decoder 20 is selected to decode ASCII characters. Visual message source 12 of course need not* be the above described terminal but may be any means of converting alphanumeric characters into a selected code with a suitable decoder 20 being selected to decode the same.

Visual message processor 14 accepts the digital data from visual message source 12 and in the usual manner will convert the digitally encoded information into a series of analog audio frequencies. To facili¬ tate the operation of receiver/demodulator 18 and bit synchronizer 19, the audio frequency which corresponds to the low binary logic level is set at 1.5 times the frequency of the audio frequency which corresponds to the high binary logic level, and that the data train bit rate generated by visual message processor 14 is

identical to the audio frequency encoding the high binary logic level. In a preferred embodiment of the present invention, the low binary logic level is chosen to have a corresponding audio frequency of 1800 Hz and the high binary logic level to have a cor¬ responding audio frequency of 1200 Hz. The data train containing these audio frequencies is applied to transmitter 15 at a rate of 1200 bits/second. Of course any audio frequencies .can be chosen, however, receiver/ demodulator 18 and bit synchronizer 19 will operate at a slower bit rate or become electronically more complex. The data train, now consisting of a series of audio frequencies, is modulated onto a carrier frequency utilizing the well known method of frequency modulation. The frequency modulated RF signal is applied to antenna 16 for transmission to personal receiver 11.

The hereinabove described message communication system shows a message being developed and transmitted by transmitting means 10 and received by personal receiver 11. ^" The message communication system can be expanded to communicate messages to a selected personal receiver or selected group of personal receivers. As hereinafter described, each receiver 11 includes an address means within decoder 20. A digitally encoded address signal precedes the message, the address signal may identify a selected personal receiver or a selected group of personal receivers. Visual message processor 14 may be a commercially available data processing and time sharing computer network, such as Ty share, Inc. The address signal as well as other hereinafter described signals, which comprise a header preceding the message, are developed by visual message processor 14. The header format as hereinafter described will enable a person skilled in the art to program the commercially available computer network to develop the header preceding the message.

FIGURE 2a shows a message portion 30 and a header 21 including a plurality of synch signals 22 for preparing personal receiver 11 (FIGURE 1) for reception of the data train, a first control signal 24 marking the end of the plurality of synch signals 22, and address signal 25a for addressing the personal receiver for which the message is intended defining an addressed personal receive-r, and, a further address signal 25b which may optionally be included in header 21, a second control signal 26 to mark the end of all address signals, a message -type signal 27 containing selected instructions for the addressed personal receiver, relative to the utilization of the message portion 30, a message length signal 28 containing information of the total character count of message portion 30, and a drift time signal 29 containing information of'the time remaining until the end of the data train.

Each synch signal 22 includes a plurality of data bits selected for maximizing the number of transi- tions between -data bits while also conveying framing information to decoder 20 of FIGURE 1. In a preferred embodiment of the present invention, each synch signal

22 contains a hexadecimal D4 or binary 11010100. The number of synch signals 22 should be at least 60 to - insure detection as hereinafter described in reference to reception duty cycle means.

The remaining signals in header 21, which will hereinafter be fully described, are all encoded by a well known, redundant binary code for detecting and correcting single bit errors occurring during data transmission. The redundant code chosen must be capable of being detected by decoder 20 of FIGURE 1. In a preferred embodiment of the present invention, all of the signals in header 21 are encoded by the well known ^' 8421 weighted Hamming code modified as hereinafter described. A typical byte 23 of header 21 includes

error correcting nibble 23a and an information nibble 23b. Each subscripted I represents an information or data bit of information nibble 23b. Each subscripted P of error correcting nibble 23a represents the re- dundant bits of the 8421 Hamming code. The method by which the Hamming code detects and corrects errors is well known in the art and need not be further described.

Following the plurality of synch signals 22 is first control signal 24 including a plurality of data bits selected so that the data bit pattern does not match the data bit pattern of synch signal 22. In a preferred embodiment of the present invention, first control signal 24 includes eight binary data bits containing a hexadecimal FF or binary 11111111. Following first control signal 24 is at least one address signal 25a for identifying a unique personal receiver or a selected group of personal receivers. Address signal 25a includes a plurality of data bits whose data bit pattern may not match the bit pattern of first control "signal 24 or second control signal 26. In a preferred embodiment of the present invention, address signal 25a includes eight bytes formatted in the hereinabove modified Hamming code from which eight information nibbles can be obtained. Header 21 may also contain a plurality of further address signals, such as address signal 256, for identifying corresponding personal receivers for reception of the same- data train. First control signal 24 also marks the beginning of each address signal following address signal 25a. Second address signal 25b is of different data bit configuration from address signal 25a. Should it be desired to include further address signals (not shown) , each further included address signal is preceded by first control signal 24. ^' Following all address signals is second control signal 26 to mark the end of all address signa

Second _, control signal 26 includes a plurality of data bits whose data bit pattern may not match the data bit pattern of first control signal 24 or any hereinabove described address signal. In a preferred embodiment of the present invention, second control signal 26 includes two bytes formatted in the hereinabove described modified Hamming code where each such byte is identical to first control* signal 24. It is not necessary that second control signal.26 include two bytes where each byte is identical to first control signal 24, since any data bit pattern may be utilized for second control signal 26 as long as it is capable of being decoded as a second control signal marking the end of all address signals. Following second signal 26 is message type signal 27 containing selected instructions for the addressed personal receiver relative to the utilization of message portion 30. In a preferred embodiment of the present invention, message type signal 27 includes one byte formatted in the hereinabove described modified Hamming code wherein the three least significant bits contain the selected instructions.

The first instruction shown as 000 in message type signal 27a represents that the following message portion 30a includes a message 30f for. the addressed personal receiver to be stored in a hereinafter described message means. Message 30f and all hereinafter described messages are developed by the hereinabove described visual message source 12 of FIGURE 1. The second instruction shown as 001 in message type signal 27b represents that the following message portion 30b includes an address signal 25c to which a hereinafter described second addressable means will be made non-responsive. As hereinafter described, each personal receiver 11 includes an address means responsive

to the hereinabove described address signals having a first addressable means responsive to an address signal uniquely identifying the. personal receiver and a second addressable means programmable by message portion 30. Message 30g is stored in the message means and contains the alphanumeric representation of address signal 25c and when displayed will advise the recipient that the second addressable means has been made non-responsive to address signal 25c. When header 21 includes message type signal 27b, address signal 25a is the only address signal allowed in, header 21 and must uniquely identify the per¬ sonal receiver or be the same as address signal 25c.

The third instruction shown as 010 in message type signal 27c represents that the following message portion 30c includes an address signal 25d to which the second addressable means will be made responsive. Message 3Oh is stored in the message means and contains the alphanumeric representation of address signal 25d and when displayed will advise the recipient that the second addressable means has been made responsive to address signal 25d. When header 21 includes message type signal 27c, address signal 25a is the only address signal allowed in header 21 and must uniquely identify the personal receiver. The fourth instruction shown as 011 in message type signal 27d represents that the following message portion 30d includes an address signal 25e and a message 30i which is stored in the message means and when dis¬ played will advise the recipient that the second address- able means has been made non-responsive to all address signals. When header 21 includes message type signal 27d, address signal 25a is the only address signal allowed in header 21 must uniquely identify the personal receiver and be repeated as address signal 25c. The fifth instruction shown as 100 in message type signal 27e represents that the following message

portion 30e contains urgent message 30 to be stored in the message means overriding the storage of other here¬ inabove described messages, should storage locations be insufficient for all messages stored in the message means.

In each of the hereinabove described message type signals 27a through 27e, the most significant bit of the information nibble was shown as X, representing that this bit may contain.0 or 1. Normally this bit will contain 0, however, should it contain 1 as shown in message -type signal 27f, a corresponding additional header 21a is inserted between drift time signal 29 and message protion 30. Additional header 21a includes at least one length of remaining header signal (LOH) 21b and additional header information signals 21c which con¬ tain selected information for the addressed personal receiver. In one embodiment of the present invention, additional header information signals 21c include 256 bytes formatted in the hereinabove described Hamming code and LOH signal 21b includes 2 bytes thereof, and contains information of the total character count of additional header information signals 21c, by representing the decimal character count in binary representation in the eight bits provided by the two information nibbles. However, should each nibble contain a hexadecimal 0, the additional header signals 21c contain 256 bytes and a further LOH signal 21d follows containing informa¬ tion of the character count of further additional header signals 21e. Following message type signal 27 is message length signal 28 which contains information of the total character count of message portion 30 and also the char¬ acter count of additional header 21a if present. Message length signal 28 includes a plurality of data bits representing the amount of storage to be utilized in the message means for message portion 30. In one

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embodiment of the present invention, message length signal ^* 28 includes 3 bytes formatted in the hereinabove described Hamming code from which 3 information nibbles can be obtained. Of these three nibbles, all but the

5 most significant bit in the first nibble are used to count the characters, allowing a character count not exceeding 2 . The most significant bit in the first nibble contains information of an immediately following data train, as hereinafter described. - _j _ _Q Following message length signal 28 is drift time signal 29 which contains information of the time remaining until the end of message portion 30 or in the event of repeated transmissions of the data train, the time remaining until the end of all repeated data 15 trains. Drift time signal 29 includes a plurality of data bits which encode the time remaining. Each personal receiver 11 includes a hereinafter described reception duty cycle means which sequentially activates the receiver for a first time period and deactivates the

20 receiver for a- second time period, and a hereinafter described control means responsive to drift time signal 29 for changing either time period commensurate with the time encoded by drift time signal 29. In a preferred embodiment of the present invention, drift time signal

25 29 includes three bytes formatted in the hereinabove described Ham in code from which 3 information nibbles can be obtained. The information nibbles of drift time signal 29 may contain a hexadecimal 0 to a hexadecimal FFF, encoding, in one embodiment of the present invention,

30 real time values of 26-2/3 ms to 109 s.

Included in message portion 30 is a parity check signal 31 which includes a plurality of data bits which represent an overall parity check of the afore¬ mentioned messages, and is developed by visual message

35 processor 14 of FIGURE 1. As hereinafter described, the addressed personal receiver performs the identical

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parity --check on the received message developing an internal parity check signal. Parity check signal 31 is compared to the internally developed signal, and if the same, the message has been received without error, and if different, a possible error exists in the message. The control means, further responsive to parity check signal 31 and operative to extend the second time period commensurate with drift time signal 29 if no error is detected, or to extend the first time period commensurate with drift time signal 29 if an error occurred allowing monitoring' of repeated transmissions of the data train, is provided. In one embodiment of the present invention, parity check signal 31 includes eight data bits of information. The most significant bit is an even parity check bit of the remaining seven bits. The seven least significant bits may contain a hexadecimal 0 to a hexa¬ decimal 7F.

FIGURE 2b shows a general format for stacking and repeating data trains. As hereinabove described, message length ^" signal 28 contains information of the presence of an immediately following data train. Message length nibbles 28a, 28b and 28c represent the three information information nibbles in the hereinabove described embodiment of message length signal 28. The most significant bit 28d of message length nibble 28a may contain either a 0 or 1. If a 0 is contained therein, the presence of an immediately following data train is verified. The control means is further responsive to message length signal 28, and more parti- cularly, bit 28d, to extend the first time period to assure reception of the immediately following data train.

Data train 32a represents an example of stacking a first data train including a first header 21, and message portion 30 with a second immediately following data train including a second header.21. ' and a

message portion 30*. Data trains 32b and 32c represent sequentially repeated representations of data train 32a. The hereinabove description of header 21 of FIGURE 2a applies equally to all of the headers shown in ^* FIGURE 2b. The only differences are in drift time signal 29 of FIGURE 2a. Header 21. includes drift time signal 29a which contains information of the time re¬ maining until the end of data train 32c. Header 21. is repeated as header 21- and 21- in data trains 32b and 32c, respectively, the only modification occurring in drift time signals 29c and 29e which both contain information of the time remaining until the end of data train 32c measured in real time from their occurrence in their respective headers. Similarly, drift time signals 29b, 29d and 29f contain information of the time re¬ maining until the end of data train 32c measured in real time from their occurrence in headers 21',, 21'- and 21' , respectively.

^• FIGURE .2c shows the format of a further sequentially transmitted data train 33 utilized by personal receiver 11 to determine if such receiver is out of range of transmitting means 10 of FIGURE 1. Data train 33 includes the hereinabove described plurality of synch signals 22 immediately followed by first control signal 24 which is in turn immediately followed by second control signal 26. Further included in data train 33 is a timing signal 34a which contains informa¬ tion of a third time period and a clocking signal 34b containing information of the date and time of the transmission of data train 33. Each receiver 11 further includes an out of range warning means for developing an alphanumeric message on display 13 of FIGURE 1 to advise the user of personal receiver 11 when such receiver is out of range of transmission means 10 of FIGURE 1. The hereinafter described out of range warning means is responsive to timing signal 34a and operative to develop

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the warning message when a transmission of data train 33 has "not been received within the time period speci¬ fied within timing signal 34a.

The message means is responsive to clocking signal 34b and operative to display an alphanumeric representation of the date and time information contained in the most recently received clocking signal 34b preced¬ ing those messages received subsequent to the reception of each clocking signal 34b. It should be noted that data train 33 is sequentially transmitted at regular time intervals, •and the hereinabove mentioned data trains containing messages are interspersed therein.

FIGURE 3 shows a more detailed schematic block diagram of receiver/demodulator 18 of FIGURE 1. Receiver 35 demodulates the incoming binary encoded data train by conventional means and applies the hereinabove described sequence of audio frequencies to the input of a phase locked loop oscillator 36. As phase locked loop oscillator 36 tracks the frequency and phase of the in- coming audio frequencies, an output is generated which is a series of electrical signals approximating the corres¬ ponding binary logic levels. By choosing the herein¬ above described relationship between the audio frequencies used to encode the two binary logic levels and the trans- mission rate of the data train, operation of phase locked loop oscillator 36 is facilitated by the phase relationship that exists between successive bits of information as encoded by the audio frequencies. The voltage controlling the voltage controlled oscillator of phase locked loop oscillator 36 is utilized as the out¬ put. In one embodiment of the present invention, phase locked loop oscillator 36 may be any commercially available phase locked loop oscillator integrated cir¬ cuit such as the 4046 commercially available from National Semiconductor.

The output of phase locked loop oscillator 36

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is applied to a signal level averager 37 for detecting the most negative and the most positive peak voltage of ^' the applied electrical signal. Averager 37 includes a capacitor 37a for storing the highest positive peak voltage occurring when a diode 37b becomes forward biased. A capacitor 37c stores the most negative peak voltage occurring when a diode 37d becomes forward biased. Two equivalent resistors 37e and 37f average the voltages stored by capacitors 37a and 37c, respectively. The node between the two resistors 37e- and 37f is at a voltage level which is the average of the stored voltage levels. In one embodiment of the present invention, capacitors 37a and 37c are 0.1 uf. Diode 37b and 37d are both commercially available IN 4148 diodes, and re- sistors 37e and 37f are 470 kohm.

A threshold detector 38 compares the applied signal from phase locked loop oscillator 36 to the applied signal from averager 37. Whenever the electrical signal applied from phase locked loop oscillator 36 is at a higher voltage than the electrical signal applied from averager 37, threshold detector 38 generates an electrical signal that corresponds to the low binary logic level. Conversely, the high binary logic level is generated when the electrical signal applied from phase locked loop oscillator 36 is at a lower voltage than the signal applied from averager 37. Threshold detector 38 may be a commercially available differential amplifier, operated with a positive supply voltage equal to the voltage encoding the high binary logic level, and with the negative supply voltage coupled to ground. A series resistance-capacitance feedback path (not shown) is connected between the output and the non-inverting input of the differential amplifier, and the electrical signal generated by phase locked loop oscillator 36 is applied to this inverting input. The output of averager 37 is applied to the non-inverting input of

differential amplifier. The output of the differential amplifier develops a series of DC voltage levels which correspond to the binary logic levels of the data train developed by visual message processor 14 (FIGURE 1) . In one embodiment of the present invention, threshold detector 38 is a commercially available RCE CA 313OA amplifier.

FIGURE..4 shows a more detailed schematic block diagram of bit synchronizer 19 of FIGURE 1. A crystal oscillator 40, which is of conventional design, generates a clock pulse train that is applied to a first binary ripple counter 41. The Q2 output of counter 41 is a lower frequency pulse train which is applied to the 12 input of a first switch 42. The Q3 output of counter 41 applies a still lower frequency pulse train to the II input of a second switch 43. The II input of first switch 42 is coupled to ground and the output of first switch 42 is applied to the 12 input of second switch 43. First switch 42 and second switch 43, both of which are of conventional design, operate so that when their respective switching input S is at a low binary logic level, the II input is enabled to the output. If their respective switching input S goes to a high binary logic level, then the 12 input is enabled to the output. The output from threshold detector 38 (FIGURE

3) is applied to the input of a pulse generator 44 for generating a pulse of a high binary logic level for a time period significantly briefer than the time period of a single data bit of information whenever there is a transition in the binary logic level between successive data bits applied to its input. Pulse generator 44 includes a common exclusive-or (EX-OR) gate with two logical inputs. The output of threshold detector 38 is applied directly to one of the inputs of the EX-OR gate, and also applied to the other input of the EX-OR gate through a time delay network. The output pulse generated

when there is a change of binary logic levels between successive data bits is of a time duration equal to the amount of time delay provided at the input of the EX-OR gate. The time delay function may be realized by apply- ing the output of threshold detector 38 through a resistor which is then applied to a common node of the second logical input of the EX-OR gate and a grounded capacitor. In one embodiment of the present invention, the time delay should be approximately 2-3% of the time period of a single data bit of information. The output of pulse gene.rator 44 is applied to the S input of second switch 43.

In the above described mode of operation, second switch 43 will normally have its II input enabled to its output which is applied to counter 45. Counter 45 divides the frequency of the incoming clock pulse train, which in the normal mode of operation, is the Q3 output of counter 41 as enabled through the output of switch 43. The divided frequency clock pulse train generated by the Q8 output of the counter 45 is applied into the S input of switch 42. The 2 output of counter 41 is enabled to the output of switch 42 for one half of the time period of the clock pulse train developed by the Q8 output of counter 45. The output of switch 42 is the clock pulse train developed by the Q2 output of counter 41 gated by the clock pulse train generated by the Q8 output of counter 45 having been applied to the S input of switch 42.

Where the time period of the clock pulse train generated by the Q8 output of counter 45 is identical to the time period of a data bit of information, ,the Q8 output of the second binary ripple counter 45 will become synchronous with the data train applied to pulse generator 44. When pulse generator 44 applies a high binary logic level to the S input of switch 43, the output from switch 42 is enabled to the input counter 45.

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In this mode of operation the next transition state of the Q8 output of counter 45 is delayed for a period of time that is equal to the time that the II input of the first switch 42 is enabled to the input of counter 45; or the next transition state of the Q8 output of counter 45 will be time shifted forward for a period of time that is equal to the time that the 12 input of the first switch 42 is enabled to the input of the second binary ripple counter 45.. By also applying the Q8 output of counter 45 to the S input of switch 42, a feedback loop is established so that synchronization will occur when the II and 12 inputs of switch 42 are sequentially enabled to the input of counter 45 for an equal period of time whenever a pulse is applied to the S input of switch 43. When synchronism occurs, the lead¬ ing edge of the pulse train generated by the Q8 output of counter 45 will occur in real time at the center of a data bit.

■ Synch s.ignal 22 (FIGURE 2) is chosen to maximize the number of transition states between successive data bits to enable the clock synchronizer to minimize, synchronization time of the Q8 output of the second binary ripple counter 45 with the data train.

The data bits are sampled by applying the out- put of the threshold detector 38 to a sample circuitry 46. Sample circuitry 46 provides means by which the applied input at input I is enabled to and stored at the output when a positive leading edge of the clock pulse train is applied to clock input C from the Q8 output of the second binary ripple counter 45. The sampling and storage means are conventional and are realized in one embodiment of the present invention by a switch and a storage .capacitor.

Oscillator 40 also applies its clock pulse train to decoder 20 (FIGURE 1); and the Q8, Qll and

Q13 outputs of counter 45 are also coupled to decoder 20.

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These plock pulse trains provide the timing for decoder 20 to execute the hereinafter described programs therein.

In one embodiment of the present invention, oscillator 40 provides a clock pulse train of 2.4540 MHz. The Q2 output and the Q3 output of counter 41 develop clock pulse trains of 613.5 kHz and 306.7 kHz, respectively. The Q8, Qll and Q13 outputs of counter 45 develop pulse- trains of 1200 Hz, 150 Hz and 37.5 Hz, respectively. FIGURE 5 shows a more detailed schematic block diagram of decoder 20 of FIGURE 1. An external on- off switch 50 enables electrical energy from an energy source 51 to be applied to a voltage regulator 52. Voltage regulator 52, which is of conventional design, applies a constant electrical voltage level to a switch 53 and an electrical energy supply line 54. Switch 53 enables the electrical energy applied at input I to the output 0 whenever its switching input S is at a high binary logic level. Switch 53 applies the electrical energy at output 0 to an electrical energy supply line

75, which supplies electrical energy to receiver/demodu¬ lator 18 and display 13 of FIGURE 1. Electrical energy supply line 54 is coupled to a central processing unit (CPU) 55 at its V input and to resistors 60 and 71. At the conclusion of the hereinafter described initialization program, the CPU 55 will generate a sleep siganl and apply such signal to a NAND-gate 59 where such signal is a high binary logic level. The second input of NAND gate 59 has applied to it an elec-. trical signal which is normally at a high binary logic level. When both inputs to NAND gate 59 are a high binary logic level, NAND gate 59 develops an electrical signal that is at a low binary logic level. This electrical signal when at the low logic level and applied to the PAUSE input of CPU 55 will cause the CPU 55 to cease operation in the execution of the instruction sets

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of the program. Also the NAND gate 59 will apply the low bihary logic level signal to the S input of the switch 53 thereby disabling the input I to the output 0. The electrical energy is removed from line 75. When the clock pulse train generated by the Q13 output of counter 45 (FIGURE 4) is applied to capacitor 61 and goes to a low binary logic level, the hereinafter described reception duty cycle activates the monitoring mode. Capacitor 61 develops a negative pulse responsive to the trailing edge of the clock pulse train, and applies said pulse- to the second input of NAND gate 59, which develops a positive pulse for application to the S input of switch 53, enabling electrical energy to the output 0 and the electrical energy supply line 75. The positive pulse is also applied to the PAUSE input of CPU 55 which then resumes execution of the instruction sets until another SLEEP signal is generated. Capacitor 61 is recharged from current through resistor 60. The cyclical -operation is hereinafter referred to as the reception duty cycle means.

During the active monitoring mode, the data train from sample circuitry 46 (FIGURE 4) is applied to a tristate buffer 63. The tristate buffer 63 accepts the data train and applies the data train to a data bus 58 which transfers the data train under program control to CPU 55, which analyzes the data prior to the data being accepted in RAM 64.

The Q8 output generated by counter 45 is ap¬ plied to an isolation capacitor 70 which develops a negative pulse upon the occurrence of a trailing edge of the clock pulse train applied to it. This negative pulse is applied to the INT input of CPU 55 which causes an interrupt subroutine as hereinafter described to be executed. This subroutine will enable the data train to be accepted onto data bus 58 and applied to

CPU 55. Capacitor 70 is recharged from a current ^^T EA

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through a resistor 71.

Whenever CPU 55 generates a memory address over an address bus 56 to be applied to RAM 64, a simultaneous signal will be generated of a high binary logical level from the WAIT output and applied to the S input of switch 68, the WAIT signal will override the external on-off switch 50, enabling a constant source of energy to be applied to the electrical energy supply line 54. The WAIT signal is necessary to allow completion of the operations of the instruction whenever the RAM 64 is being addressed to protect its memory contents. In one embodiment of the present invention, CPU 55 is a commercially available RCA 1802 micropro¬ cessor and the employment and programming of said processor is well documented in the art. ROM 57 is preferrably any commercially available CMOS read only memory integrated circuit with the capability of storing at least four-thousand ninety-six eight bit words. RAM 64 is preferrably anycommercially available CMOS random access memory ^" integrated circuit with the capability of storing at least one-thousand twenty-four eight bit words. Energy source 51 is preferrably a NiCd battery of approximately 6.2 v .and energy source 65 is prefer¬ rably an Li battery of at least 2 v. The NiCd battery is preferred for its nearly constant voltage output prior to becoming discharged whereas the Li battery is preferred because of its long shelf life since this battery is only used to supply microwatts of power to RAM 64 when the NiCd is fully discharged or disabled from voltage regulator 54. Voltage regulator 52 prefer¬ rably provides a well regulated output voltage of five volts regulated within +0.25 volts while supplying up to 10 ma of current. Should power from the voltage regula¬ tor drop below the voltage of energy source 65, diode 66 becomes forward biased and diode 67 becomes reverse biased whereby the RAM 64 is effectively nonvolatile.

Visual alphanumeric display 13 may be any electronic digital display which has the capability of converting binary encoded characters into readable alphanumeric characters. In the preferred embodiment of the present invention, display 13 provides a readout of twenty characters by utilizing five Litronix DL1414 display modules of four characters apiece. A character is enabled to the display by first addressing that character stored in RAM 64, applying said character to data bus 58, and applying the character to the display module to be displayed at the location on said module determined by a memory address applied from address bus 56. In this mode of operation the display appears to the CPU 55 as additional memory locations. Alert functions, such as a beeper, may also be incor¬ porated into the circuitry as virtual memory locations. These techniques are well known in the art and need not be further discussed.

It is within the scope of the invention to provide a hard ^" copy record of the messages. A message may be retrieved from RAM 64 in the usual manner. A character printer may be connected to the appropriate output port (not shown) of the CPU 55.

The structure of the personal receiver 11 of FIGURE 1 has been described as well as a great deal of its operation. But the sequence of events that have been discussed above have been controlled by the programs recorded permanently in ROM 57 of FIGURE 5. These programs are given in exhibit "A" hereto for a particular embodiment of the system being described, and a flow chart of the operations of the central processing unit 55 programmed by the programs of Exhibit "A" is given in FIGURES 6, 1 ,and 8. By referring to the program of Exhibit "A" and the flow charts of FIGURES 7, 7 and 8, the programmed operation of CPU 55 can be fully under-. stood in great detail. It will be noted that the

location (LOC) column on the left hand side of the pro- gram of Exhibit "A" identified memory locations of ROM 57 which are also liberally identified on the flow charts of FIGURES 6-8. Each line of the program identifies the contents of sixteen consecutive memory locations beginning with the location in the LOC column. All representations are hexadecimal numerals, and recognized by the RCA 1802 microprocessor preferred in the present invention.. But so that the general reader will obtain an understanding of the program of CPU 55, its flow charts of FIGURES 6-8 are described generally.

FIGURE 6 shows a block diagram illustrating the logical sequence of initialization instructions executed by CPU 55 of FIGURE 5. Request box 100 indicates that two internal registers of the CPU 55 are being dedicated as the main program counter register, which will contain the address of the program, instructions contained in ROM 57 (FIGURE 5) , and the data pointer register, ^' which will contain the address of the locations of stored data ^' within RAM 64 (FIGURE 5) . Concurrently with the selection of registers, the INT input of CPU 55 is disabled until the initialization routine is completed, during which no data is to be applied to the tristate buffer 63 (FIGURE 5) . Once the main program counter register has been initialized, the sequence of instructions of request box 102 will clear and set the remaining internal registers of CPU 55. These registers are utilized by various subroutines, ^' hereinafter described. Decision box 104 indicates that RAM 64 will be scanned in the locations reserved for an address means. If a universal address code is not located in RAM 64, request box 106 indicates that the universal address code will be obtained by CPU 55 generating a memory address over address bus 56 (FIGURE 5) to be applied to a location in ROM 57 containing the universal address

code. The universal address signal is then placed on ^• data bus 58 (FIGURE 5) , and applied to RAM 46 upon the generation of a memory address by CPU 55 specifying the location where such universal address code is to be stored. The sequence of operations of request box 106 are not executed if the universal address code has heretofore been stored in RAM 64.

The CPU 55 executes the instruction set of request box 108 clearing working locations in RAM 64 for various subroutines hereinafter described.

After specified locations in RAM 64 are cleared, the instructions of request box 110 indicate that data is read from ROM 57 and stored in RAM 64. This data initializes values for processing by subroutines, hereinafter described, controlling the aformentioned reception duty cycle means.

Upon the completion of the instructions con¬ tained in request box 110, the control of CPU 55 becomes governed. by the main executive routine (EXEC) illustrated by. program box 112.

FIGURE 7 shows a block diagram illustrating the logical sequence of instructions of the main executive routine of program box 112 of FIGURE 6. Request box 120 indicates that the INT input to CPU 55 (FIGURE 5) is disabled; furthermore, the execution of the EXEC logic is synchronized with the negative pulse generated by capacitor 61 (FIGURE 5) , the operation of which has heretofore been fully described.

Input-output box 121 indicates that CPU 55 will generate a high binary logic level at the SLEEP output. Upon the occurrence of the negative pulse generated by capacitor 61 and the responsive pulse thereto applied to the PAUSE input of CPU 55, execution of the EXEC logic is synchronized with said pulse. The timing for the reception duty cycle means is derivative from said pulse, and furthermore, during the active

- ^< gORE OMPI

portion thereof, EXEC logic is executed, determining if any action should be taken, either under program control or user control. The program controlled actions, hereinafter described, are generally internal management subroutines whereas the user controlled actions occur when the user desires information, such as the display of a message stored in RAM 64 (FIGURE 5) . After the above actions arǤ completed, if necessary, a decision is made whether the reception duty cycle means should sequentially activate the receiver 11 for the first time period and deactivate receiver 11 for the second time period (determined by Q13) , or whether control means should be operative to extend the first time period to receive a data train. The EXEC logic governing the control means is cycled for each character of incoming data and will continue until the entire data train has been monitored, providing that the header 21 (FIGURE 2a) contains an address signal 25 to which personal receiver 11 is responsive ^" .' The. EXEC logic executed during the first time period of the reception duty cycle means is set forth in detail as follows.

Request box 122 indicates that visual alpha¬ numeric display 13 (FIGURE 1) will be supplied battery power during the active portion of the reception duty cycle. However, the data inputs to display 13 will be in an unknown state. To prevent the unwanted display of extraneous characters, the instructions of request box 122 are executed to cause binary encoded blanks to be retrieved from ROM 57 (FIGURE 5) and applied to display 13.

Upon completion of the display blanking, CPU 55 must then determine the sequence of events, if any, to be perfomed within personal receiver 11. The events to be performed are determined by the instructions of request box 124. A plurality of register or memory locations within CPU 55 or RAM 64, respectively, are

decremented each time the instructions of request box 124 are executed. Should any of these locations be decre¬ mented to zero, additional instructions are executed to indicate that a certain event is to be performed. In one embodiment of the present invention, there are five events controlled by these locations which serve as program controlled timers. The first event is controlled by a sleep/wake timer which contains an initial value determined by request box 110 (FIGURE 6) , and which provides the reception duty cycle means with related information concerning the first and second time periods. In the normal mode of operation, the sleep/wake timer is equal initially to the time duration of the plurality of synch signals 22 (FIGURE 2) divided by a constant determined so that the timer will be decremented to zero at least one time during the time period required for the transmission of synch signals 22. The event performed is the active monitoring of possible data trains.

A second event is controlled by the out-of- range timer, being an ^• out-of-range warning means, which upon being decremented to zero will warn the user of personal receiver 11 that that personal receiver 11 is out of range of the transmitting antenna 16 (FIGURE 1) . The out-of-range timer is initialized by the instructions of request box 110 (FIGURE 6) and this initial value will be restored or modified upon the reception of data train 33 (FIGURE 2) , hereinabove described.

The third event is controlled by the drift timer, the value of which is responsive to and initially equal to drift signal 29 (FIGURE 2) . A transmission system 10 (FIGURE 1) may transmit sequential, repeated data trains. The received message portion 30 (FIGURE 2) may contain uncorrectable errors in transmission which can be corrected by EXEC logic by comparing the received data with new data of a repeated transmission. Active monitoring of repeated data trains will be maintained

until the drift timer is decremented to zero, which signifies end of all transmissions of the data train, or until the received message contains no errors in which event the second time period is extended commensurate with drift signal 29. In the latter situation, the

EXEC logic increments the sleep/wake timer by the value remaining in the drift timer, and the control means is deactivated during the remainder of the repeated transmissions of ^' data trains which are not necessary when the received message contains no errors. The drift timer in combination with the sleep/wake timer define the control means.

The remaining events controlled by timers are for internal management of sequencing the rate at which characters of messages are applied to display 13 or the rate an audible alert, such as a beeper, will be acti- • vated. The described function occurs when the timer is decremented to zero.

Upon completion of the instructions of request box 124, control ^' of CPU 55 is governed by the instructions of request box 126, which are executed only when a mes¬ sage, either received and stored in RAM 57 or pre-stored in ROM 57, is to be applied to display 13. The decision controlling execution of these instructions is governed by the data generated by the execution of these in¬ structions of request box 128. A plurality of manually operable external switches on personal receiver 11 generates signals which are applied directly to input ports (not shown) of CPU 55. The instructions of request box 128 perform the function requested by the activated switch. In one embodiment of the present invention, four external switches are utilized. Activa¬ tion of the first switch causes execution of instructions necessary to retrieve the first received message stored in RAM 64 to be displayed on display 13. The second switch causes execution of the logic necessary to

OMPI

"WIPO

display a pre-stored message in ROM 57 to be displayed should the EXEC logic determine that one of the pre- stored messages is appropriate, such as the out-of-range message hereinabove discussed. Additional pre-stored messages are discussed hereinafter. Logic responsive to the third switch will rotate the display order of received messages in RAM 64 enabling the recipient of messages to selectively view any message contained in RAM 64. The fourth switch clears an active display or stops an active alert(s) . The fourth switch, when activated simultaneously with the first switch, will erase the last displayed message from RAM 64, enabling selective deletion of any message contained therein. The switches in combination with RAM 64 define a message means.

Upon the completion of the instructions of request box 128, the EXEC logic must determine if the personal receiver 11 should be placed in the first time period of the reception duty cycle means. Decision box 130 contains instructions to decide whether the sleep/ wake timer, described above, has been decremented to zero, and if so, personal receiver 11 is placed into the active ■ portion (first time period) of the reception duty cycle means. During this active portion, the INT input to CPU 55 will be enabled to allow data to be applied to the tristate buffer 63 as controlled by the interrupt service routine, hereinafter described. However, only the pos¬ sible transmission of synch signals 22 is monitored during the usual active portion of the reception duty cycle means. When synch signals 22 have been recognized, the first time period is changed by the control means, to receive in sequence, the remaining signals of header 21.

Should decision box 130 determine an event is to be performed based on the hereinabove described timers, the instructions of request box 132 are executed.

The events are queued and processed so that only one such

event i_s performed each time the instructions of request box 132 are executed should two or more of the afore¬ mentioned timers be simultaneously decremented to zero. Each timer has a corresponding queue which is set upon the timer being decremented to zero. Each queue, in one embodiment of the -present invention, is a binary data bit contained in an internal register of CPU 55 dedicated for queue processing.

Upon completion of the instructions of request box 132, the instruction of request box 134 may be executed if a hard copy printer is connected to the personal receiver 11 and more particularly to the appropriate output (not shown) of CPU 55. Execution of the logic of request box 134 is repeated until each data bit of message has been addressed at its location in the message means placed on the data bus 58 and stored in the accumulator of the CPU 55. When a character of message text has been formed, the contents of the accumulator of CPU 55 is applied to a hard copy printer. Upon, completion of the instructions of request box 134, CPU 55 determines if the interrupt service routine, hereinafter described, has made data available for processing by the EXEC logic of request box 136. Data is available for processing upon the reception of a synch signal 22 (FIGURE 2) , and thereafter upon the reception of a completed character of any signal within header 21 or message portion 30. The instructions of request box 136 is state dependent on the logic of request box 138. The state dependency enables the EXEC program to determine if the incoming data is one of the plurality of signals contained in header 21 of message portion 30. The state enables the control means to determine whether receiver 11 should be activated to receive the next header signal. In one embodiment of the present invention, the state assignments are negative when no data train has been received and becomes positive upon

recognition of a synch signal 22. Each of the remaining signals, when recognized, increments the state. The state determines which signal is to be expected in the incoming data train. The control means is responsive to the state and operative to extend either the first or second time periods determined by the state assignment. The state comprises, generally, a plurality of binary logic levels, and preferrably is an eight bit value located in a dedicated ^' register internal to CPU 55. When three of said synch signals 22 have been recognized, the first time period of reception duty cycle means is extended and receiver 11 is enabled for the continuous reception of the remaining data train. The instruction set of request box 136 is executed every time the interrupt service routine, hereinafter described, makes data available for processing.

The logic of request box 136 is also able to detect and correct errors in transmission of the header 21 for those signals which are format encoded in the aforementioned _, Hamming code. Errors in said message portion 30 are detected by said parity check signal 31 described above. Instructions of request box 136 will also generate a parity check signal internal to personal receiver 11. The internally developed parity check signal and received parity check signal 31 are then com¬ pared at the completion of the reception of the data train. If the two signals are not equal, and no subsequent repeated transmissions of the data train are forthcoming, the recipient of message 30 will then be warned that the viewed message contains an unspecified error. However, if repeated data trains are forthcoming, each character of the new message portion 30 will be compared with the stored characters of the previous message, each character corrected if necessary, and a new internal parity check signal will be generated. When the parity check signal 31 and the internally generated parity check signal are

equal, the stored message is treated as if error free. The cςmparison of repeated data trains and more parti¬ cularly the message portion 30 thereof, is continued until both parity check signals are equal or until the drift timer is decremented to zero. The instructions for generating the parity check signal is contained in locations OCDA through OD44 of request box 138. Thus, the control means is responsive to parity check signal 31. ^• The instructions of request box 136 is also responsive to the length of message signal 28 and deter¬ mines the ^" amount of free memory available in the message means in which to store the incoming message portion 30. However, logic of request box 138 is also responsive message type signal 27e (FIGURE 2) which develops a state that will allow the message storage locations of the message means to be overwritten with a message text 30j (FIGURE 2) .

After the instructions of request box 136 have been executed, a ^' decision must be made if the first time period is to be maintained or terminated and the second time period extended as indicated by decision box 140. The decision if dependent on the state value generated by the logic of request box 138, and should the state value indicate that further data is expected, as herein¬ above described, the first time period is extended. A unit timer, hereinafter described, is queried, and control of the CPU 55 is governed as indicated by decision box 142. However, if the state value at decision box 140 indicates that the second time period can be resumed, the control of CPU 55 is returned to the beginning of the main executive routine and more particularly to request box 120. RAM 64 in combination with the instruc¬ tions of request box 136 also define the address means. Whenever capacitor 70 (FIGURE 5) generates a negative pulse and such pulse is applied to the INT

input of CPU 55 when the EXEC routine has enabled inter¬ rupts, to occur, the control of the CPU 55 is governed by the interrupt service routine of FIGURE 8. The interrupt service routine enables the incoming data train to be serially applied to tristate buffer 63 until one character is formed. This character is then compared with the known synch signal 22 configuration. When synch signal 22 has been received and recognized, the interrupt service- routine will signify that data is available to the EXEC routine and more particularly to request box 136 of FIGURE 7. The instructions of the interrupt service routine is hereinafter set forth in detail.

Request box 150 indicates that contents of the registers internal to CPU 55 are stored in RAM 64 for future reference. The registers are restored to these values upon completion of the interrupt service routine . to enable return of the execution of the EXEC logic at the location where interrupted. After the contents of the registers have been saved, control of CPU 55 is governed by the instructions of request box 152 which indicates that the current data bit of the data train has been applied to tristate buffer 63 and stored in a working location of RAM 64. A decision must be made by CPU 55 as indicated by decision box 154, which inquires the state value generated by request box 138 (FIGURE 7) . Should the state value be equal to zero, the instructions of the interrupt service routine determines if the accumulated data bits have formed synch signal 22. If synch signal 22 is found as indicated by decision box 156, the state value is incremented to one, as indicated by request box 158. Request box 160 is then executed to indicate to the EXEC logic that data is available for processing by request box 136 (FIGURE 7) .

Should the instructions of decision box 154

-indicate that the state value is not equal to zero, the state .is reexamined by decision box 162 to determine if the state value is positive or negative. In one embodiment of the present invention, a negative state value indicates that no data train is being received by personal receiver 1 and a positive state value indicates that the EXEC logic is expected to receive further data as hereinabove described.

After the state value has been determined by decision box 162, and- assuming it is found to have a positive state value, a decision is made whether the accumulated data bits have formed the next character of the data train. Decision box 164 indicates that, should a character have been formed, this new character is to be made available to the EXEC logic for processing. Otherwise, data bits are collected and stored in the working locations of RAM 64 until the next character has been formed.

After the above decisions have been made, and the appropriate ^" instructions executed, the instructions of request box 166 are executed. These instructions decrement the unit timer which includes a plurality of binary logic levels. In one embodiment of the present invention, the unit timer includes eight bits of informa- tion contained in an internal register of CPU 55 (FIGURE 5) . The unit timer is decremented each time the inter¬ rupt service routine is entered, and therefore responsive to the Q8 output of second binary ripple counter 45 (FIGURE 4). Preferrably, the unit timer has an initial value of eight that is decremented to zero, which indicates that the unit timer fired, and reset to eight again.

After the unit timer has been decremented, a decision is made, as indicated by decision box 168, whether the unit timer is at a zero or non-zerό value. Should the unit timer be at a non-zero value, control

OMPI

of CPU 55 is governed by the instructions of request box 170. -The logic of request box 170 restores the registers of the CPU 55 to the values contained therein at the moment of entry into the interrupt service reoutine. Control of the CPU 55 is returned to the EXEC routine of FIGURE 7.

The decision, should the unit timer have been decremented to zero, will cause execution of the logic of request box 172 which restores the unit timer to its high value. Request box 174 indicates that the unit timer has fired and this information is saved for the determination to be made by decision box 142 of FIGURE 7.

The above logical flow charts of FIGURES 6, 7 and 8, have been described with respect to a preferred embodiment therof, but it will be understood that the invention is entitled to protection within the full scope of the claims which follow the appended computer program marked as Exhibit "A".

OMPI 7

3 ^(~ βJFββ- v M 89 C0 07 08 ri 0C St 0β At F8 04 88 σ« β.β»«97 FE C8 00 78 E0 70 20 92 8C F8 FA AC 0C FA IE

*» ^• *♦!fe ⁾ =52 97 FE FE 94 FA El Fl B6 FA 02 32 3A 84 32 2£

2E 99 FA 58 89 91 A6 97 FA BF 87 30 3C F8 E5

0430=AC 0C 32 3C 99 C6 F9 10 B9 C8 33 22 C0 05 00 99

0440=FA 08 89 9E Bβ 8E AS øε FE FE 33 53 08 FA OF 58

0450--%lB IB 18 92 SC F8 EA AC EC 88 73 9Θ 73 F8 FF 5C ø46ø=3β Cl 86 3A 72 99 FA 08 F9- 01 B9 F8 10 SB 91 AS

0470=30 53 96 FA 02 3A F5 87 FB 02 A7 F4 38 F5 87 FA

3A 86 F8 01 38 82 A6 00 øe FE Fε 33 3F BC

AC EC 72 FA 07 52 aε F4 AE E2 9 74 BE øε FE 38 3F F8 10 BE 98 AE 30 3F 99 FA 18 F9 04 B9

0480=96 FA OF 86 FB 09 B8 Fa 50 A8 92 BC F8 εs AC 91

0 ^* -*C0=5C 91 2C 5C 2C 5C 87 FA FC A7 17 94 FA 02 3A 08

0400=F8 01 A6 97 FA BF 87 00 97 F9 4v) 87 F8 02 A4 91

92 8A F8 FF AA F8 14 5A D0 øε FA 20 3A 3F 99

04F0=FA 08 F9 20 89 00 F0 B0 00 εø 90 A0 C0 80 FF FF

0b00=85 F6 C3 07 70 99 32 EF FE FE 38 37 FA 58 3A 37

0bl0=97 FA 20 3A 37 97 FA 40 3A 10 86 3A 37 9 FA BF

0b20=89 87 F9 10 A7 92 BC F8 Ftb AC εc F8 20 73 91 73

0b30=F8 01 73 91 73 30 EF 99 FA 08 32 75 99 FA F7 89

0b 0=89 F6 3B 67 FE A9 92 BA 96 FA 10 3A 47 F3 εs AA

0b5 = A FA FE F9 02 5A 87 FA F0 FB 10 32 63 87 FA IF -

056 ^* 0= 24 A7 99 F9 40 B9 F8 Fl AA 4A 52 0A 2A 2A A

»b7ø=73 02 5A 30 EF 99 FA 20 32 F2 99 FA 17 3A F2 84

0380*FC 03 38 F2 97 FA 60 3A F2 92 8A F8 εβ AA BF _9 ^* - ^)* =8C ΘE AF AC 0C FE FE 33 08 1C iC IC εc 72 F 38 øbA0=90 FE 33 CO 2C 7B 72 5F IF 72 5F IF 72 5F IF 38

4C 5F FE 38 sø FE 38 A8 92 BC Fa 2 AC 8F 73

0bC0=9F 5C 99 FA a* 3A E5 1A 0A F9 Eid 30 εø F8 cø 5F

0bD =F8 10 BE F8 04 AE 30 89 0A F9 02 5A 1A 0A F9 cø d=)E0»5A 99 F9 04 89 99 FA 5F F9 03 a-j 4 F9 20 84 cø

0bF0=07 08 92 BC 84 3A EF 97 FA 40 3A EF 99 FA 14 32

0600=71 C4 C4 C4 C4 99 FA 10 32 27 Ft εs AC 0C 3A 10

9 10=99 FA EF 89 FE 33 7B 89 F9 02 A. 30 78 52 91 AA

0620=F8 00 BA BS 02 30 33 F8 E6 AC 91 AA F8 09 BA øc

0630=32 60 52 F6 CF 1A F4 CF 1A F6 CF U F6 CF 1A F6

0640=CF 1A F6 CF 1A F6 CF 1A C4 8A A8 F8 07 88 2 08 0650=F3 5C 0A Ad F8 09 BB 96 FA 02 3A 44 08 FB 00 32

0660=78 F8 01 A6 30 78 97 F9 40 87 94 30 63 IC F8 00

0670=8A 0C 3A 32 9. FA F8 89 C0 07 08 99 FA 02 C2 03

0680=C8 92 8C F8 Efc AC E2 9E BA aε AA 4A 1A Fε Fε 38

0690=97 F8 02 5C 52 30 EA 99 F6 33 9F 0A FA 2C 5C 2A

06A0=2A 30 83 1A 0A 2A 52 8A F4 A8 0A FA 07 52 9A 74

068tf=8A 88 AA 0A FE FE 33 EA FE 38 A3 94 FA 20 3A C9

»6C0=99 FE 33 EA 9 FA 02 32 01 9A aε 8A Aε 99 Fε 33

EXHIBIT A

UBSTITUTE SHEET CMPΓ

0600=EA 99 F9 40 89 87 FA IB A7 0C F9 80 5C 96 FA 02

06E0=32 EA 99 F9 80 89 87 F9 04 A7 89 FA 50 32 F3 52

06F0=0C Fl 5C IC Fd C0 5C 92 B8 F8 ε3 cø 0F 06 FF FF

*7ø0=01 02 04 08 lø 20 40 80 97 FA 40 32 70 87 F6 3B

3710=17 86 3A 70 27 30 ιε 94 52 ε2 86 F3 32 70 80 3A

0/20=27 99 FA 14 C2 01 aε 94 A6 92 3A F8 FF AA 80 32

0730=34 90 30 60 øa Fε 38 49 91 A6 97 FA BF B7 99 FA

0740=14 3A 70 99 F* 02 39 30 70 0A 3A 58 48 FB 00 32

0/50=52 28 F8 14 5A 17 F8 IE A6 30 70 Fa 08 AO 08 FB

0760=00 3A 68 5A F8 00 30 60 0A FF 01 5A 48 20 76 80

0770=E0 71 C0 61 3tt 7A C4 C4 C4 61 εø 70 20 84 FB

0/80=FC 32 03 as F4 7A CB 08 33 96 Fε 38 C9 92 BC F8

0790=07 AC 4C SA 0C AA 2A 8A 5C 52 2C 9A 5C Fl 2C C6 7A0=82 5C 2F 9F 52 8F Fl 3A FF 96 FA 7F B6 cø 08 01 ø/B0=FE 33 B7 78 82 30 01 7ε 7E 7E 7ε FA 07 A3 F8 0F

07C0=88 08 52 9b F3 FA 0F 30 01 8b FA F0 3A S0 95 FA

0700=0F 52 84 A3 rε 33 FF F8 0A AA sa 08 A8 84 FE 33

0/E0=FI 84 FF 09 38 F8 1A FF 07 38 FB 1A FF 0C 38 FB

07F0»1A FF 04 38 r ^~ i 1A FF IB 38 FB 1A * 8A θ« Ot 30

0800=23 92 8F F8 Ob AF 4F FB 01 3A 10 89 FA 40 32 ID

0ttl0=0F FA 07 FF 0b 33 10 FC 40 A4 cø 07 02 82 A4 97 øa20=FA OF B7 7A εø 7i 00 85 F6 F6 8b FA FC A5 7_ 00

0830=38 33 78 92 8C F8 OF AC 4C 8A 4C AA 4C B8 4C A3

0840=^2 8A E2 F7 A8 98 52 9A 77 88 88 FF 0F AS 98 7F

0650=00 38 FE 38 5A 89 F9 10 30' 'SO 89 FA A9 18 98

0d60=5C IC 88 5C 39 6E 7A 84 FB 38 32 1A 30 10 84 AA

0870=32 79 FE 38 82 FB F8 32 B2 97 FA 50 3A 82 8A 3A

0680=88 94 FB 0b 3A 82 F8 FF A4 30 90 FB F 3A 98 14

0890=92 BC F8 εε AC F8 00 5C 86 3A B2 97 FA 0F 3A B2

06A0=99 3A 82 87 FA 08 3A B2 94 F6 32 82 85 FA 08 C2

0680=00 69 C0 00 90 F8 00 Bl F8 20 Al BC F8 13 82 F8

08C0=FE A2 F8 10 8£ F8 04 A 91 A6 B7 A9 A7 F8 FF A4

0bO0=F8 16 AC F8 2A 5C 80 BA 2A 9A ^' 3A 08 90 AC 5C 92

06C0=βC B8 F8 OF AC F8 0F 8F Ft F9 AF F8 00 AS εs 0F

08F0*F3 32 F4 78 4F 73 FB 7F 3A EF 98 5C IC cø 09 AA β β ^β *S0 45 10 50 19 25 34 08 2A 40 4F 52 45 2A 00 80

- ^<* >10=2A 45 52 52 4F 52 2A 00 tø 2A 40 45 40 20 46 55

0920=4C 4C 2A 00 8k) 2A 50 41 52 54 49 41 4C 20 40 53

0.30=47 2A 00 80 2A 53 45 52 56 49 43 45 20 52 4b 51

0^40=27 44 2A 00 8_ 2A 4ε 4F 20 40 S3 47 53 2A 00 30

0950=2A 55 52 47 4b 4£ 54 20 40 53 47 2A 00 80 2A 4F

0 60=55 54 20 4F 44 20 52 41 4 47 4S 2A 00 30 2A 49 20 52 41 4fc 47 45 2A 00 80 2A 40 53 47 20 4C 53 54 2A 00 80 2A 40 45 40 20 4C 4F 57 2A 00

0990=80 2A 49 44 20 40 41 58 2A 00 80 2A 40 53 47 20

0 A0=43 4C 45 41 S2 45 44 2A 00 80 31 80 37 B5 30 B

0S«0=88 SC Fθ 8F 58 F8 cø sε ιc 9ε 5C IC aε 5C 08 FB

0*C0=8F 3A Cb F3 40 A9 19 F8 FF AC εc 91 73 8C FB ε

0*00=3A C8 F3 F2 AC 90 73 73 73 73 73 91 73 F8 03 B9

0-£0=F8 20 86 C0 00 69 92 60 00 εc 72 Fl 32 ε*» F 3A 2C F0 FF 01 5C 60 F0 FF 01 73 Fl 60 30 ε FF 8-1 40 4A- 4A 83 83 83 C7 F0 F7 F0 F7 F0 F7 F0

0A10=09 12 23 31 4*> 50 55 66 38 94 A8 A8 26 AF CC 01

0A20=6F 6F S8 67 71 70 70 70 70 70 70 7F 9A 90 C3 OC oc ε2 DC ε oc 2 ε6 F4 Fε Fε 08 C6 88 B8 08

0A4fc>=31 47 02 FB 04 32 51 91 A4 00 31 sa 02 FB 04 3A

0A50=55 F3 04 A4 00 FB 0Θ C 24 00 89 FA 07 A9 97 FA

SUBSTITUTE

87 92 8C F8 εo AC 91 sc IC sc F8 36 A4 92 BF

3A70=F8 02 AF 91 5F 2F 91 5F 8F FF 06 AF 0F FB 8F 3A

0A80=76 14 00 92 8C εc 89 FA 23 32 A7 F8 D4 AC 96 FA

0A90=40 32 9A 02 5C 96 FA BF 86 00 96 F9 40 86 02 F3

0AA0=32 A7 78 02 F9 80 52 84 F6 38 εs F8 03 AC 02 FB

0AB0=0F 3A Ci 34 Fβ 05 3A BC F8 IC A4 00 F8 7F cø 08

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