Title:
METHOD FOR ACCESSING MIRRORED SHARED MEMORIES AND STORAGE SUBSYSTEM USING METHOD FOR ACCESSING MIRRORED SHARED MEMORIES
Document Type and Number:
WIPO Patent Application WO/2013/140459
Kind Code:
A1
Abstract:
According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories. As a result, data can be read from the shared memories speedily by accessing respective main memories in the respective processors.
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Inventors:
TANAKA KATSUYA (JP)
TAKADA MASANORI (JP)
KUDO SHINTARO (JP)
TAKADA MASANORI (JP)
KUDO SHINTARO (JP)
Application Number:
PCT/JP2012/002007
Publication Date:
September 26, 2013
Filing Date:
March 23, 2012
Export Citation:
Assignee:
HITACHI LTD (JP)
TANAKA KATSUYA (JP)
TAKADA MASANORI (JP)
KUDO SHINTARO (JP)
TANAKA KATSUYA (JP)
TAKADA MASANORI (JP)
KUDO SHINTARO (JP)
International Classes:
G06F11/16; G06F11/20
Foreign References:
| US7340555B2 | 2008-03-04 | |||
| US6341332B2 | 2002-01-22 | |||
| JP2000181891A | 2000-06-30 | |||
| US20110167189A1 | 2011-07-07 | |||
| JP2000010901A | 2000-01-14 | |||
| US6341332B2 | 2002-01-22 | |||
| JP2000181891A | 2000-06-30 | |||
| US20110167189A1 | 2011-07-07 |
Other References:
JACK REGULA, USING NON-TRANSPARENT BRIDGING IN PCI EXPRESS SYSTEMS, 2004, pages 1 - 30, XP002686987
"PCI Express Base Specification, Revision 3.0, Section 6.14.", PCI-SIG, 10 November 2010 (2010-11-10), pages 546 - 553
JACK REGULA, USING NON-TRANSPARENT BRIDGING IN PCI EXPRESS SYSTEMS, 2004, pages 4 - 30
"PCI Express Base Specification, Revision 3.0, Section 6.14.", PCI-SIG, 10 November 2010 (2010-11-10), pages 546 - 553
JACK REGULA, USING NON-TRANSPARENT BRIDGING IN PCI EXPRESS SYSTEMS, 2004, pages 4 - 30
Attorney, Agent or Firm:
PATENT CORPORATE BODY DAI-ICHI KOKUSAI TOKKYO JIMUSHO (10-5 Shiba 4-chome, Minato-k, Tokyo 14, JP)
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