Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
METHOD FOR ACCOMMODATING SMALL MINIMUM DIE IN WIRE BONDED AREA ARRAY PACKAGES
Document Type and Number:
WIPO Patent Application WO2004012262
Kind Code:
A3
Abstract:
An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included

Inventors:
LANE RYAN
REYES EDWARD
VEATCH MARK
GREGORICH TOM
Application Number:
PCT/US2003/023405
Publication Date:
April 08, 2004
Filing Date:
July 25, 2003
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
QUALCOMM INC (US)
International Classes:
H01L23/498; (IPC1-7): H01L23/498; H01L23/538; H01L25/065
Foreign References:
US5691568A1997-11-25
US5545923A1996-08-13
US5898213A1999-04-27
US6407456B12002-06-18
Download PDF:
View/Download PDF      PDF Help



 
Previous Patent: A POWER/GROUND CONFIGURATION FOR LOW IMPEDANCE INTEGRATED CIRCUIT

Next Patent: ELECTRONIC PACKAGE SUBSTRATE WITH BACK SIDE, CAVITY MOUNTED CAPACITORS AND METHOD OF FABRICATION THE...