BOYD, Geoffrey, Arthur, Coleridge (5210 Terner Way, Apt. 307, San Jose, US)
| CLAIMS 1. A method of addressing a specific device in an array of devices addressable by a signal exceeding a threshold, the method comprising the steps of providing a signal conductor to which the devices of the array are linked, inputting a first signal to a first location on the conductor thereafter inputting a second signal to a second location on the conductor after a time delay chosen such that the first and second signals interfere at a location on said conductor corresponding to the specific device, thereby generating a signal exceeding a threshold which addresses the specific device linked to the conductor at that location. 2. Method according to claim 1, wherein said signal conductor is an electrical conductor and said first and second signals are electrical signals. 3. Method according to claim 1 or claim 2, and comprising the step of compensating for transmission line losses and/or dispersion. 4. Apparatus comprising: an array of devices addressable by a signal exceeding a threshold and linked by a signal conductor; and a signal generator configured to input a first signal to a first location on the conductor and, after a time delay, a second signal to a second location on the conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined device, thereby generating a signal exceeding a threshold which addresses the predetermined device linked to the conductor at that location. 5. Apparatus according to claim 4 and comprising two signal conductors between which the array of devices is connected . 6. Apparatus according to claim 4 or claim 5, wherein the devices are memory cells. 7. Apparatus according to claim 4 or claim 5, wherein the devices are light-emitting devices. 8. Data storage apparatus comprising a first array of addressable light-emitting devices a light-sensor for generating a signal in response to light emitted from any of said light-emitting devices, and a second array of regions located in the light path between said first array and said light sensor and in registration with the light-emitting devices of said first array, the transparency of the regions corresponding to the data to be stored. 9. Data storage apparatus according to claim 8, wherein 5 the first array is arranged substantially parallel to the second array. 10. Data storage apparatus according to claim 9, wherein the light sensor comprises a planar waveguide arranged 10 substantially parallel to the second array. 11. Data storage apparatus according to any one of claims 8 to 10, wherein the light-emitting devices are be configured to emit light only when subject to an input 15 signal exceeding a threshold. 12. Data storage apparatus according to claim 11, wherein the input signal is a voltage signal. 20 13. Data storage apparatus according to any one of claims 8 to 12, wherein the device comprises a signal conductor to which the light-emitting devices are connected, and a signal generator configured to input a first signal to a first location on the conductor and a second signal to a 25 second location on the conductor after a time delay relative to the first signal such that the first and second signals interfere at a location on said conductor corresponding to a device which it is desired to actuate. 14. Method of retrievably storing data in an array comprising the steps of: depositing material at points in the array 5 corresponding to the data to be stored, the property of the material being such that, when an array point is electrically excited, an electrical signal emanating from that point will depend on whether said material is present at that point; and 10 providing a sensor to measure an electrical signal emanating from any point in the array when said point is electrically excited. 15. Method according to claim 14, wherein said material 15 is deposited in fluid form. 16. Method according to claim 14 or claim 15, wherein the material has the property of electrical resistance. 20 17. Method according to claim 14 or claim 15, wherein the material has the property of a threshold device. 18. Method according to any one of claims 14 to 17, wherein the step of depositing material includes the step 25 of depositing one of at least two types of material each having a different said property. 19. Apparatus comprising an array of devices addressable by a signal exceeding a threshold and linked by a signal conductor; and a signal generator configured to input a first signal to a first location on the conductor and, after a time 5 delay, a second signal to a second location on the conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined device, thereby generating a signal which addresses the 10 predetermined device linked to the conductor at that location ; wherein a device, when addressed, affects an electric signal emanating from that device; the apparatus further comprising at least one sensor 15 to measure said electrical signal. 20. Apparatus according to claim 19, wherein a device has an electrical resistance such that, when addressed by a voltage, an electrical signal in the form of a current 20 flows through the device, to the picked up by the sensor. 21. Apparatus according to claim 19 or 20, wherein the sensor has a threshold. 25 22. Apparatus according to claim 19 or 20, wherein the device is a threshold device. 23. Apparatus according to claim 19 or claim 20, wherein the device has switchable properties. 24. Apparatus according to claim 23, wherein the device is switchable by application to the device of an electrical signal of greater magnitude than that ordinarily used to address the device 25. Apparatus according to claim 24, wherein the device comprises chalcogenide glass. 26. Data storage apparatus comprising a plurality of data storage cells each comprising an array of memory devices addressable by a signal exceeding a threshold and linked by at least one signal conductor, and a signal generator configured to input a first signal to a first location on a conductor and, after a time delay, a second signal to a second location on a conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined memory device, thereby generating a signal exceeding a threshold which addresses the predetermined device linked to the conductor at that location . 27. Data storage apparatus according claim 26, wherein said plurality of data storage cells arranged in an array . |
DESCRIPTION
TECHNICAL FIELD
The present invention relates to methods of addressing a specific device in an array, in particular methods of addressing an electronic data storage device or memory. The invention also relates to electronic memory structures .
BACKGROUND ART
Whilst the concept of digital memory is guite simple, namely an array of cells which can be in one of two data states 0, 1 such that these states can be individually addressed for reading (and writing) data, the practical implementation of very large scale memory is far from simple . Semiconductor technology has given rise to several implementations of such memory devices where the 0,1 states are realized by a variety of physical attributes. For example in Dynamic Random Access Memory (DRAM) - the charge on a capacitor; state of a digital flip-flop in Static Random Access Memory (SRAM); the high and low resistances of Masked Read Only Memory (ROM) ; the floating gate transistor arrays of UV light Erasable Programmable Read Only Memory (EPROM) , Electrically Erasable and Programmable Read Only Memory (EEPROM) and FLASH EEPROM. In these cases, the memory is typically fashioned in a two dimensional matrix which is addressed by asserting digital data onto the rows and columns of the matrix. Data is read by monitoring a threshold current or voltage to decide whether the stored element previously written is to be interpreted as a data bit, 0 or 1. Memory is said to be Non-Volatile when the device can retain its written states when power is removed, as is the case, for example, with EPROM, EEPROM, ROM and FLASH memories.
In the Printed Electronics arena there are many emergent and competing non-volatile memory candidates . Typically a two dimensional matrix is addressed by rows and columns, and in its simplest form, one transistor is reguired for each row and each column. Such high speed transistors have to be provided either as a printed organic semiconductor or as a silicon semiconductor via an external interconnect system. However, such an addressing scheme reguires a large number of interconnections - 2000 drive interconnects typically being reguired for the 1000x1000 matrix in a lMegabit (Mb) non-volatile memory cell .
DISCLOSURE OF INVENTION
According to a first aspect of the present invention, there is provided
A method of addressing a specific device in an array of devices addressable by a signal exceeding a threshold, the method comprising the steps of
providing a signal conductor to which the devices of the array are linked,
inputting a first signal to a first location on the conductor
thereafter inputting a second signal to a second location on the conductor after a time delay chosen such that the first and second signals interfere at a location on said conductor corresponding to the specific device, thereby generating a signal exceeding a threshold which addresses the specific device linked to the conductor at that location.
By means of only two signal inputs, it is possible to address any one of many - potentially thousands or millions - of devices attached to the conductor. This is to be contrasted with the conventional memory structures mentioned above reguiring the intersection of two conductors for each device.
The addressing schema relies on the delays of electromagnetic signals inherent in transmission lines driven at multiple points and the superposition of such signals to exceed a threshold at a given position (address) within the transmission line. Advantageously, the accuracy of the addressing and hence resolution and memory size can be improved by properly taking into account transmission line losses and dispersion. A one dimensional (1-D) transmission line conductor may be extended to two dimensions (2-D) obviating the need for micro-strip conductor patterning.
This first aspect of the invention also provides apparatus comprising:
an array of devices addressable by a signal exceeding a threshold and linked by a signal conductor; and
a signal generator configured to input a first signal to a first location on the conductor and, after a time delay, a second signal to a second location on the conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined device,
thereby generating a signal exceeding a threshold which addresses the predetermined device linked to the conductor at that location.
The predetermined device is predetermined by virtue of input data to the signal generator. Such input data may come from outside the apparatus or may be generated by the signal generator itself.
The apparatus may comprise two signal conductors between which the array of devices is connected, thereby increasing the number of addressable locations by the power of two. The devices may be memory cells or light-emitting devices .
According to a second aspect of the present invention, there is provided
data storage apparatus comprising
a first array of addressable light-emitting devices a light-sensor for generating a signal in response to light emitted from any of said light-emitting devices, and a second array of regions located in the light path between said first array and said light sensor and in registration with the light-emitting devices of said first array, the transparency of the regions corresponding to the data to be stored.
The transparency of a region will determine whether, when a light-emitting device is addressed, the emitted light is picked up by the light sensing device. This provides a mechanism for reading the data (typically a binary '1' or 'Ο') stored in the region. The transparency (or lack thereof) of a region is easily effected by printing methods, e.g. by the offset litho printing of ink onto a transparent substrate to create a non-transparent region and the non-printing of ink to create a transparent region. This second aspect of the invention therefore offers a low-cost way of storing data.
In preferred embodiments, the first array of addressable light-emitting devices and the light-sensing device can also be manufactured using printing, i.e. deposition of electronically-active materials in fluid form. As such, they may be arranged substantially parallel to the second array of regions to create a laminate. Alternatively, light can be fed by a planar waveguide to a sensor located to one side of the apparatus.
A third aspect of the present invention provides a method of retrievably storing data in an array comprising the steps of:
depositing material at points in the array corresponding to the data to be stored, the property of the material being such that, when an array point is electrically excited, an electrical signal emanating from that point will depend on whether said material is present at that point; and
providing a sensor to measure an electrical signal emanating from any point in the array when said point is electrically excited.
Such a method employs deposition as the data recording mechanism. This can be easy/cheap to implement, particularly in applications where deposition by printing is already used for other, e.g. decorative, purposes.
The property of the deposited material may be electrical resistance, in which case, when electrically excited by a voltage, an electrical signal in the form of a current through said material will be determined by said resistance .
Alternatively, the material may be a threshold device such as a transistor or diode. The method may employ two or more types of material having different properties. When excited, one material may have relatively high current flow and the other relatively low current flow.
The second and third - data storage - aspects of the invention are advantageously addressed using the method of the first aspect. In such a scheme the interconnects between the printed electronics memory array and the silicon driving and sensing circuitry are minimized from the 2000 conventionally reguired for 1 Mb to circa 4 interconnects. Such a reduction in interconnect reguirement and complexity makes this printable nonvolatile memory device very low cost and amenable to large scale manufacturing processes.
Thus, in a device according to the second aspect, the light-emitting devices may be configured to emit light only when subject to an input signal exceeding a threshold. The input signal may be a voltage signal.
The device may comprise a signal conductor to which the light-emitting devices are connected, and a signal generator configured to input a first signal to a first location on the conductor and a second signal to a second location on the conductor after a time delay relative to the first signal such that the first and second signals interfere at a location on said conductor corresponding to a device which it is desired to actuate.
Apparatus e.g. manufactured according to the third non-optical aspect above comprises an array of devices addressable by a signal exceeding a threshold and linked by a signal conductor; and
a signal generator configured to input a first signal to a first location on the conductor and, after a time delay, a second signal to a second location on the conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined device,
thereby generating a signal which addresses the predetermined device linked to the conductor at that location ;
wherein a device, when addressed, affects an electric signal emanating from that device;
the apparatus further comprising at least one sensor to measure said electrical signal.
The device may have an electrical resistance such that, when addressed by a voltage, an electrical signal in the form of a current flows through the device, to the picked up by the sensor, which may itself have a threshold.
Alternatively, the device may be a threshold device such as a transistor or diode.
Re-writable apparatus may be obtained by use of a device having switchable properties. Switching may be achieved by application to the device of an electrical signal of greater magnitude than that ordinarily used to address the device (but which can nevertheless be applied using interference of first and second time-delayed signals as discussed above) . One suitable device may comprise chalcogenide glass, which can be changed between two states (crystalline and amorphous) of different resistivity by the application of a heating pulse.
The first aspect of the invention can also be applied to conventional memory structures, e.g. row-column architectures defining memory cells. Instead of having a diode or transistor, each memory cell can itself comprise an array of memory devices e.g. of the kind described above and addressable by a signal exceeding a threshold and linked by at least one signal conductor, and a signal generator configured to input a first signal to a first location on a conductor and, after a time delay, a second signal to a second location on a conductor such that the first and second signals interfere at a location on said conductor corresponding to a predetermined memory device, thereby generating a signal exceeding a threshold which addresses the predetermined device linked to the conductor at that location.
BRIEF DESCRIPTION OF DRAWINGS
An embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:
Figures 1A and B are diagrammatic views of a transmission line;
Figure 2 is a graph illustrating the amplitude and phase characteristics of the transmission line of figures 1A and B;
Figure 3 is a schematic of a further transmission line ;
Figure 4 is a graph illustrating the variation of output with time at node 16 of figure 3;
Figure 5 illustrates the variation of output with time at nodes 6 to 16;
Figure 6 illustrates the progression of pulses along an ideal transmission line;
Figure 7 illustrates the progression of pulses along a lossy transmission line;
Figure 8 illustrates the progression of pulses along a lossless line with dispersion;
Figure 9 illustrates the progression of pulses along a line having some dispersion but with pulse pre- egualisation ;
Figure 10 is a schematic illustration of a first embodiment of the invention;
Figure 11 is a schematic view of a second embodiment of the invention;
Figure 12 is a schematic view of a third embodiment of the invention;
Figure 13 is a circuit diagram illustrating the response of a small signal diode;
Figure 14 shows the variation of current and time for the circuit of figure 13;
Figure 15 is a sectional view of a fourth embodiment of the invention;
Figure 16 is a schematic of the transmission line eguivalent of figure 15; Figure 17 is a sectional view of a fifth embodiment of the invention;
Figure 18 is a schematic of the transmission line equivalent of figure 17;
Figure 19 is a sectional view of a sixth embodiment of the invention;
Figure 20 is a schematic of the transmission line equivalent of figure 19;
Figure 21 is a sectional view of a seventh embodiment of the invention;
Figure 22 is a schematic of the transmission line equivalent of figure 21;
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
In order to show how transmission lines can be used to address memory, it is useful firstly to consider a transmission line as a constant-k ladder structure consisting of a large number (infinite in the limit) of identical interconnected inductors and capacitors in ladder form as shown on figure 1.
Such a structure acts as a delay line, the total delay, T d , of the structure being approximately:
T d = n*SQRT (L*C) where n is the number of LC sections. The delay per section, t n is given by:
SQRT (L*C) It can be shown using image impedance technigues that the impedance of the transmission line is given by: Ζ(ω) = SQRT ( L/C ) *SQRT (1- (L*C*6) 2 /4))
= Z 0 *SQRT (1- (L*C*6) 2 /4))
Where Z 0 = SQRT (L/C) is the characteristic impedance of the line. The impedance becomes imaginary for freguencies above a critical freguency given by: ω α = 2/SQRT(L*C)
The amplitude and phase characteristics of the ladder structure elements are shown in Figure 2. When a transmission line is terminated with a passive resistor egual to its characteristic impedance Z 0 then there are no reflections at the terminations.
The superposition of voltages to exceed a threshold at a given point along the transmission line, in accordance with the present invention, can be understood by reference to figure 3, which is a schematic of a damped transmission line consisting of 32 ladder sections. Drivers VG1 & VG2 inject timed voltage pulses into the opposite ends of the transmission lines and the results are monitored at the nodes 01 to 16 using respective voltmeters VM01 to VM16. The characteristic impedance of the circuit was 100Ω.
Figure 4 illustrates the output with time at node 16 which, being at the edge of the line, is the worst case. Figure 5 shows the output with time for node 16 and other nodes 06 to 15.
This is further illustrated in figure 6 which shows the progression over time of two pulses introduced simultaneously at opposite ends of an ideal transmission line. The solid and dotted traces of figure 6A show the two pulses at t=0 and t=2 respectively. The solid and dotted traces of figure 6B show the two pulses at t=3 and t=4. The solid trace of figure 6C shows how, at t=5, the two pulses constructively interfere at definable location along the line (the midpoint in the example shown) to create at a definable peak having amplitude (of 1.0) which is significantly greater than that (of 0.5) of the individual pulses. The dotted trace of figure 6C and the solid and dotted traces of figure 6D show the subseguent separation of the pulses at t=6, t=7 and t=8 respectively.
Figures 7 again shows pulse progression, this time with a lossy transmission line (modelled by a low pass filter) . At t=5 (solid line of figure 7C), the two pulses again constructively interfere at the same the midpoint, albeit with a peak that has a lower amplitude (of around 0.8) and that is broader and less precise. The simulation nevertheless illustrates that when a transmission line is properly terminated it can be driven at both ports to create a sufficiently well defined superposed threshold pulses even when the line is damped by the internal resistance of inductors. In the example of figure 7, a suitable threshold might be midway between 0.8 and 0.5, say 0.65.
It follows that the invention is suitable for implementation in printed electronics, which typically have higher resistivity than conventional copper. Typical ½ OZ copper traces on Printed Circuit Board (PCB) for strip lines and micro-strip lines have a surface resistance of approximately 1.0 mQ-square compared to printed conductors (e.g. polymer conductors such as PEDOT) which have a surface resistivity of approximately 25-100 mQ-sguare .
However, to ensure that threshold detection is reliable, the total trace damping resistance of the transmission line should preferably be less than the characteristic impedance.
The desired resolution of the transmission line determines the necessary minimum delay between pulses launched into the transmission line. It also effectively guantizes the analogue transmission line into the constant-k ladder structure of the simulations. It further influences the width of the pulses launched into the transmission line: to ensure that only one location on the line is addressed, the reconstructed width of the threshold pulse in the time domain should preferably be less than the delay of the minimum resolved ladder section . Where the dielectric for the capacitance in the transmission line is partially semiconductor, as in the printed memory devices described hereafter, this will be lossy and will lead to normal dispersion at higher frequencies. Skin effects in the conductor trace will also lead to dispersion of the internal inductance portion of the ladder network. Such dispersion effects can mean the higher frequencies suffering less delay. As illustrated in figure 8 for a lossless line with dispersion (modelled by an all pass filter), this results at t=5 (solid line in figure 8C) in a broad pulse occupying two normal time units, resulting in poorer time and location precision.
Such effects can be analyzed and corrected in real world applications by network analysis and Fourier methods. Network analysis allows the actual transmission line values to be identified, while Fourier analysis will give insight into the best means of processing the data, e.g. by filtering and pre-emphasis means to obtain very sharp pulse waveforms in the time domain at the threshold address with improved signal at threshold to the floor or noise level. The finite element method can also be used to analyze and correct for delay and dispersion. Figure 9 shows modelled pulse progression in a practical line having moderate dispersion and some loss but where good precision for time and pulse shape has been achieved by pre-equalising the pulses prior to driving the line, in the case shown by means of a stepped pre-emphasis. This measure essentially returns both time precision and pulse amplitude to the ideal condition of figure 6.
Figure 10 is a schematic illustration of a first, one-dimensional embodiment of the invention. Transmission line 170 is supplied with signals at both ends by drivers 175,180. As explained above, the delay between the respective signals is chosen such that they meet at a specific point along the line, e.g. point P in figure 10, and constructively interfere. The resulting signal exceeds a threshold, thereby actuating the device at the location of the coincidence, e.g. actuating a memory cell 185 between the line 170 and a ground line 190. To give a 1Mb memory addressing scheme, such a transmission line as evaluated in the schematic simulations above would need to resolve 1 million locations.
Figure 11 is a schematic illustration of a further embodiment utilizing two arrays of horizontal (X) and vertical (Y) transmission lines 200,210 mutually spaced in the depth (Z) direction. The horizontal transmission lines 200 are commonly driven from either end by drivers 220,225 whilst the vertical transmission lines 210 are commonly driven from either end by drivers 230, 235. The signals applied to the X lines are of opposite sign to those applied to the Y lines such that, where superposition of signals in the X lines coincides with superposition of signals in the Y lines, the resulting potential difference exceeds a predetermined threshold and actuates the device (e.g. actuates a memory cell) at the location of the coincidence . Addressing for a given tx and ty drive delay occurs along a diagonal with a train of events separated by the delay t n of a section. A specific location can be read by gating the sense amplifier or storing the entire train of events in a shift register on the silicon controller IC.
The device of figure 12 has the advantage that no strip line patterning of the conductor layer is reguired, the device having instead a rectangular - in this case sguare - transmission layer or panel 250. Two-dimensional potential (more properly electromagnetic) 'waves' are 'launched' into the layer 250 via pads 260. The layer is also terminated on all four sides 255 with its characteristic impedance Z 0 in order to minimize edge reflections .
The shapes and positions of the signal input pads 260 can be optimized by computation using typically Fourier and finite element methods for electromagnetic signals to realize the best superposition of waves for threshold voltages in the time domain.
In many of the memory devices discussed in the introduction above, the memory elements can be considered as small signal diodes. The short time pulse response of a small signal diode can be simulated in the time domain by the circuit of figure 13 having the typical local and inductance values below
Z 0 =SQRT(L/C) = 50 Ω
L = 10 nH C= L/Z 0 ^2= 4 pF
SQRT ( L*C ) = 200
1/ (pi*tn) = 1.59 The corresponding timing plots for the circuit are shown in Figure 14. It will be seen that the threshold current response (AMI) is sharper than the voltage (VMl), suggesting that threshold current sensing is the most appropriate measure for a local voltage stimulus .
Such current sensitive mechanisms are to be found in light emitting diodes, organic light emitting materials and organic semiconductors and figure 15 shows one embodiment of a memory structure according to a second aspect of the invention and employing such a material.
A substrate 300, e.g. of PET or coated board, has a first cathode layer 310, e.g. of a metallic conducting material such as indium tin oxide (ITO), a second layer 320 of light emitting material, e.g. organic (OLED) material such as small molecule or polymer, and a third, transparent anode layer 330, e.g. a hole injecting material such as poly ( 3 , 4-ethylenedioxythiophene ) (PEDOT) .
Layers 310,320,330 define a light emitting device 360, any region or pixel of which can be excited to emit light by subjecting it to a voltage greater than a certain threshold using the mechanism outlined above. The corresponding dual ported transmission line addressing schematic is shown in figure 16, the anode layer 330 being connected to the signal drivers 340,350 and the cathode layer 310 being connected to earth.
Above the light emitting device 360 is located a light sensing device 400 made up of a photovoltaic polymer layer 410 sandwiched between a lower layer 420 of conducting 5 transparent polymer, e.g. PEDOT, and an upper metallic conducting layer 430.
Between the emitting and sensing devices 360 and 400 is located a further data layer 370 having opague and transparent regions or pixels 380,382 and 390,392 10 respectively. The regions may be provided by the printing of ink.
When a particular region 380 ' , 382 ' , 390 ' , 392 ' of the emitting device 360 is excited to emit light, the opague/transparent status of the corresponding region
15 380,382,390,392 of the data layer determines whether sensing layer 400 receives that light. This provides a mechanism for reading the status of any particular region of the data layer. It follows that binary data can be retrievably stored in layer 370 by the printing of a
20 pattern of opague regions onto an otherwise transparent layer .
A micro-replication topology 325 may advantageously be incorporated into the active interface of the PLED/OLED layer 320 and transparent anode layer 330 to increase the 25 local electrical field to enhance photon emission. The scale of the micro replication is generally smaller than the scale of the memory cell and does not therefore reguire alignment . Figure 17 shows an alternative embodiment of the device of figure 15 in which the light sensing layer is replaced by an optical light guide 440 which directs any light passing through the data layer 370 to a remote silicon photo detector indicated schematically at 450. The addressing mechanism - illustrated in the schematic of figure 18 - remains the same as in the previous embodiment .
An advantage of the optical memory constructions discussed above with regard to figures 15 and 17 is that a light sensing mechanism effectively isolates the electrical noise generated by the pulsed currents in the transmission line addressing schema.
Another advantage of the optical structure is that it lends itself to extending the method to create changeable electronic displays with and without memory with an essentially unchanged physical structure having typically the same number of pixels as memory cells.
Figure 19 illustrates a display structure without memory, elements common to the embodiments of figures 15 and 17 being designated by common reference numerals. The photo detector layers and circuitry of the aforementioned embodiments are omitted and a regular pattern 500 is printed on the memory layer 370 to define pixels 510. The display is addressed again using the transmission line addressing schema as illustrated in figure 20. The display is kept on by continually refreshing the pixel data at a rate higher than human flicker detection, typically 50 to 70Hz .
Such a system is closer to a cathode ray tube (CRT) system than modern flat panel displays in that a single location is addressed at a given time - like the electron beam of a CRT. Grey scale is obtained by varying the addressing dwell time at a particular pixel location. The embodiment shown is monochrome but the structure can be readily converted to colour by partitioning red, green and blue pixels. Megapixel grey scale displays display structures may reguire extensive address refreshing.
Low information content displays can easily be accommodated simultaneously with memory on a single structure. In such an embodiment, the top layer waveguide is configured to act in a dual-purpose, reduced-efficiency mode which allows both viewing and light collection.
However, figure 21 illustrates an alternative, non- optical memory cell structure, with figure 22 showing the corresponding addressing schematic. Features common with earlier embodiments are indicated by common reference numerals .
In this embodiment, the OLED threshold mechanism is replaced by a layer 600 of organic semiconductor transistor or diode elements 610. Such elements are discussed e.g. in McCulloch et al, Nature Materials, Vol. 5, pp328-333, April 2006 and Berggren et al, Nature Materials, Vol. 6, pp3-5, January 2007) . As indicated by different shading 612, 614, different types of element corresponding to binary '0' and '1' are used to record data in the layer 600. Such non-optical methods rely on relative amount of electrical current flowing through threshold devices such as transistors and diodes or material whose resistance can be made variable.
In one embodiment, one type of element (e.g. corresponding to '1') may be provided by an active diode or transistor (as known having a low resistance that results in a relatively high current flow when addressed. The other type of element (e.g. corresponding to Ό') may have a higher threshold resulting in a relatively low current flow when addressed, or may not be patterned at all .
The addressing scheme can be used to change the phase of the material at a specific location in the layer. One suitable material is chalcogenide glass, which changes between two states - crystalline and amorphous having different resistivities - on the application of heat. A larger voltage pulse may be used to locally heat a particular location on the substrate and change its state, with a lower level voltage pulse being used to read the location. Such an arrangement allows the memory to be re ¬ writable. A similar scheme may be used in the optical arrangements discussed above, with a phase change giving rise to differing optical properties, e.g. near- transparent to near opague instead of relatively high to low electrical resistance.
The sensing mechanism uses the differential scheme of figure 20 in which an actuated threshold mechanism 610 unbalances the currents in a differential transmission line. This unbalance will differ depending on the type of element that has been deposited at the location being addressed. A differential amplifier 650 is used for detection so as to minimize the common mode electrical noise .
In operation it may be that the printed memory devices such as the polymer diodes and transistors are too slow to respond at the narrow pulse widths for high resolution of memory. Repeatedly stimulating an addressed location with short pulses will have the effect of extending the perceived pulse width by the slow device, effectively creating a guasi-standing wave at the threshold location.
Though the addressing scheme is intrinsically analogue, it can be given the certain accuracy of the digital domain by patterning the memory cells on a scale smaller than typical pulse widths in the time domain. This will ensure that the full reinforced voltage pulse (resulting from the interference of the two signals) is experienced over the entire width of the threshold device, ensuring maximum output. The sensing apparatus can be set to respond only to such maximum output, thereby reducing sensitivity to any other noise in the system.
The optical memory structures using the 2-D Transmission Line addressing scheme also have the advantage of an entirely homogenous PLED or OLED structure with the non-volatile data memory patterning accomplished by printing opague and transparent patterns corresponding to 0's and l's using conventional inks and printing technigues. This optical approach lends itself to low cost high speed manufacture of roll to roll thin films which can later be converted onto printable paper card or PET substrates. It is to be contrasted with the non-optical memory structures of the kind disclosed in figure 19 and 20 where the organic semiconductor needs to be microscopically patterned into the non volatile data array memory by selective printing of the organic semiconductors. This reguires a scheme for electrically writing the memory, leading to further complexity reguiring further microscopic patterning.
The 2-D structure of figure 10 also lends itself to manufacture by thin film roll-to-roll manufacturing technigues. When implemented with the optical memory structures of figures 13 and 15, manufacture may be broken down into three modular processes: Process 1: Roll-to-Roll Thin Film Manufacture of amalgamated layers of the structures
Step a. The polymer (PLED) or other organic (OLED) light emitting active layer 320 is located on the metallized or conducting microreplicated polymer film 310;
Step b. The photovoltaic layer 410 or waveguide layer 440 is located on the metallized or conduction polymer film 330; Process 2j Roll-to-Roll Conversion to flexible
Transmission Panels;
Step a. Cut laminate from Process 1, step a to form a panel 250 and bond it to a substrates 300, e.g. a printable substrate such as paper, board or PET.
Step b. For each panel 250, make sure that the transmission line is properly terminated, e.g. by printing the characteristic terminating impedance Z 0 at its edges 255. Optimized drive terminals 260 and pads for connection of an integrated circuit can also be printed;
Step c. Pick and place integrated circuits on the connection pads;
Process 3: Roll-to-Roll Final Device Manufacture
Step a. Print the data layer 370 or pixel pattern 500,510. This non-volatile memory pattern may include error correcting, redundancy and alignment data bits. Standard printing eguipment can be used, including printing presses, professional inkjet printers, laser printers, and personal desktop inkjet printers. However, conventional printing presses may offer highest speed manufacture. Ink jet printing, though slower, will result in finer resolution and thus higher memory density.
Step b. The threshold layer and the detector layer from earlier steps are then laminated to the data layer to make a non volatile memory device. Because no alignment is reguired the process can be efficiently carried out in normal print facilities The above method allows mass manufacture with high throughput of low cost devices suitable for storing high information content for disposable industrial and consumer electronics products.
By including thin batteries and audio circuitry and actuators on the card substrate a complete Audio Visual device can be created. If radio freguency communication is included in the Silicon IC then the device can function as a high information content storage device.
In the embodiments described above, the addressing and sensing of threshold events is conveniently implemented at the 45nm to 90nm scale available in silicon integrated circuits. In contrast, the transmission lines and associated memory structures are conveniently manufactured by the deposition ( colloguially 'printing') of electronically-active fluids over typical areas of 10mm to 100mm sguare with printable line widths of the order of lOum to 50um.
However, the addressing schema of the present invention is egually applicable to sub-micron implementation e.g. on silicon. At such a scale, the timings would be tighter and the resolution thus lower - e.g. 10 's to 100 's of locations in each two-dimensional X, Y panel giving memory resolutions in the range 100 bits to 10K bits .
Micron scale silicon is also possible, with amorphous silicon being deposited on flexible substrates such as PET or stainless steel foil to make active electronics materials .
The addressing schema can also be used in combination with conventional X-Y (row-column) architectures employing one diode or transistor per memory cell. For example, conventional patterning can be used to coarse grain the memory into cells at the mega & giga word level and the addressing schema of the present invention can be used to further fine grain the cells to the kilo-bit per word level .
In one embodiment, the X-Y matrix patterning gives coarse grained 2-D cells which are then further resolved in the XY plane without further patterning. For example at the lOOnm line-width node, cells of lum x lum are patterned with local drive and sense transistors (e.g. like a TFT LCD) and then each of these lum x lum cells is resolved down to circa 100-lK memory locations using the addressing schema of the invention and thus without further patterning.
Alternatively, the addressing schema may be applied in a third Z dimension perpendicular to the X-Y matrix of the conventional architecture . A corresponding read-write process may employ two threshold levels as per CD Read/Write .