Title:
METHOD FOR ANALYZING WAFER
Document Type and Number:
WIPO Patent Application WO/2017/122921
Kind Code:
A1
Abstract:
A method for analyzing a wafer, of an embodiment, comprises the steps of: forming an oxide layer on a wafer; forming a film on the oxide layer; applying stress to the wafer having the oxide layer and the film; measuring the intermediate flatness of the wafer to which stress has been applied; heat-treating the wafer, to which stress has been applied, at a first predetermined temperature; measuring the final flatness of the heat-treated wafer; and estimating the flatness of the wafer by using the intermediate and/or final flatness.
Inventors:
LEE CHUNG HYUN (KR)
LEE SEUNG WOOK (KR)
HAM HO CHAN (KR)
KIM JA YOUNG (KR)
LEE SEUNG WOOK (KR)
HAM HO CHAN (KR)
KIM JA YOUNG (KR)
Application Number:
PCT/KR2016/013132
Publication Date:
July 20, 2017
Filing Date:
November 15, 2016
Export Citation:
Assignee:
LG SILTRON INC (KR)
International Classes:
H01L21/66; H01L21/02; H01L21/324
Foreign References:
| KR20110050405A | 2011-05-13 | |||
| KR100877102B1 | 2009-01-09 | |||
| KR20020030458A | 2002-04-25 | |||
| KR100334706B1 | 2002-09-05 | |||
| US6174740B1 | 2001-01-16 |
Attorney, Agent or Firm:
PARK, Young Bok et al. (KR)
Download PDF: