INCORPORATION BY REFERENCE

[0001] This present disclosure claims the benefit of U.S. Provisional Application No. 61/638,692, "Clockless Asynchronous SARADC" filed on April 26, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

[0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] Various electronic devices include an analog-to-digital converter (ADC) as a signal processing component. The ADC samples an analog signal and converts the sampled analog signal to digital values. The digital values can be further processed using digital signal processing techniques.

SUMMARY

[0004] Aspects of the disclosure provide an analog-to-digital converter (ADC). The ADC includes a comparator module and a digital-to-analog converter (DAC). The comparator module is configured to compare a first voltage sampled from an analog signal and a second voltage output from the digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison. The DAC is configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage.

[0005] In an embodiment, the comparator module is configured to select one of a pair of output signals based on the result of the comparison and output the pulse in the selected output signal. Further, in an example, the comparator module is configured to avoid a pulse output from the non-selected output signal at the same time with the selected output signal.

[0006] According to an embodiment of the disclosure, the comparator module includes a reset control circuit configured to reset circuits in the comparator module in response to the pulse. The comparator module resets at the same time the DAC settles the second voltage. 3 038445

2

[0007] According to an aspect of the disclosure, the DAC includes multiple switching units corresponding to digital bits of a digital value, and the multiple switching units are enabled in a chain to switch based on pulses output from the comparator module. In an example, the switching unit is configured to enable a next switching unit when its state has been revolved.

[0008] According to an aspect of the disclosure, the comparator module does not output a clock signal.

[0009] Aspects of the disclosure also provide a method. The method includes comparing a first voltage sampled from an analog signal with a second voltage settled by a digital-to-analog converter (DAC), generating a pulse to indicate a result of the comparison and enabling a switching unit in the DAC corresponding to a digital bit to switch a state based on the pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0011] Fig. 1 shows a block diagram of an integrated circuit (IC) chip example 100 according to an embodiment of the disclosure;

[0012] Fig. 2 shows a diagram of a comparator module example 210 according to an embodiment of the disclosure;

[0013] Fig. 3 shows a timing diagram example 300 according to an embodiment of the disclosure; and

[0014] Fig. 4 shows a flow chart outlining a process example 400 according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0015] Fig. 1 shows a block diagram of an integrated circuit (IC) chip example 100 according to an embodiment of the disclosure. The IC chip 100 includes an analog to digital converter (ADC) 101 to sample an analog signal and convert the sampled analog signal into digital values. The IC chip 100 can include other suitable circuit components (not shown), such as an analog signal processing circuit (not shown) to prepare the analog signal, a digital signal processing circuit (not shown) to process the digital values, and the like. The IC chip 100 can be a system-on-chip (SOC), or can be a part of any suitable system, such as a computer, a laptop, a Blu-ray player, a sensor device, an automobile, and the like. 3

[0016] In the Fig. 1 example, the ADC 101 is a successive approximation type ADC that, for each conversion of a sample of the analog signal, performs a number of binary searches through all possible quantization levels before finally converging upon a digital value, such as a number of bits corresponding to a voltage level, or a current level of the analog signal. The ADC 101 includes a comparator module 1 10 and a digital-to-analog converter (DAC) 150 coupled together as shown in Fig. 1.

[0017] In the Fig. 1 example, the comparator module 1 10 receives a first voltage \½ corresponding to a sample of the analog signal for conversion, and a second voltage V _DA c output from the DAC 150, and compares the first voltage VIN with the second voltage V _DA c- Based on the comparison, the comparator module 1 10 outputs a pulse in one of a first pulse output C ₀ and a second pulse output Q. In an example, when the first voltage VI is higher than the second voltage VD _A C, the comparator module 1 10 outputs a pulse in the second pulse output Q, and when the first voltage V _M is lower than the second voltage V _D AC, the comparator module 1 10 outputs a pulse in the first pulse output Co. In an embodiment, the comparator module 1 10 is configured such that, a comparison result is output in the form of a pulse from one and only one of the first pulse output Co and the second pulse output Cj .

[0018] Further, in an embodiment, the comparator module 1 10 is configured to reset the circuits in the comparator module 1 10 by itself after a comparison to prepare for a next comparison. In the Fig. 1 example, the comparator module 1 10 includes a reset control circuit 120 to reset the circuits in the comparator module 1 10 in response to each pulse in the first and second pulse outputs Co and C _\ . For example, when the first pulse output Co outputs a pulse, the reset control circuit 120 resets the circuits in the comparator module 1 10, and when the second pulse output C] outputs a pulse, the reset control circuit 120 resets the circuits in the comparator module 1 10. In an example, the comparator module 1 10 takes a reset time to reset the circuits in the comparator module 1 10, and takes a comparison time to make the comparator decision. It is noted that the comparison time for the comparator decision may vary. In an embodiment, once enabled, the comparator module 1 10 repetitively performs a reset operation and a comparison operation before being disabled.

[0019] The DAC 150 receives the two pulse outputs C ₀ and C| , and progressively resolves bit values of a digital value corresponding to the voltage level of the analog signal. According to an embodiment of the disclosure, the DAC 150 includes a plurality of chained circuit units, such as B9 to BO in Fig. 1, corresponding to the bits of the digital value. For example, the digital value has ten bits. The circuit unit B9 corresponds to a most significant bit bit-9 of the digital value, the circuit unit B8 corresponds to bit-8 of the digital value, so forth, the circuit unit B l corresponds to bit- 1 of the digital value, and the circuit unit BO corresponds to a least significant bit bit-0 of the digital value. Each circuit unit receives the first and second pulse outputs Co and C _l5 and a control signal from a previous circuit unit in the chain. In an embodiment, the control signal has an enable state that enables the circuit unit to operate in response to the first and the second pulse outputs Co and Ci, and has a disable state that does not allow the circuit unit to operate in response to the first and the second pulse outputs Co and Further, the enable state can be passed along the chain to enable the circuit units B9 to BO one by one to resolve their states in response to pulses in the first and second pulse outputs Co and

[0020] In an example, each circuit unit includes one or more switching circuits configured to switch to a state corresponding to a bit value based on the first and second pulse outputs Co and Ci once the circuit unit is enabled. For example, once enabled, the circuit unit can switch to a logic "0" state corresponding to a binary value "0" when the first pulse output C ₀ has a pulse, and can switch to a logic "1" state corresponding to a binary value "1" when the second pulse output C I has a pulse. When the enable state is passed along the chain one by one, the circuit units B9 to B0 resolve the states corresponding to the bit values of the digital value based on the first and second pulse outputs Co and Ci .

[0021] Further, the DAC 150 converts the states of the circuit units B9 to B0 to the second voltage V _D AC- According to an aspect of the disclosure, the DAC 150 takes a logic delay time for switching the states of the circuit units B9-B0 in response to a pulse in the first and second pulse outputs Co and Ci, and takes a settling time for settling the second voltage VDAC to a level corresponding to the states of the circuit units B9-B0. In an example, the DAC 150 is suitably configured that a sum of the logic delay time and the settling time is about the same as the reset time of the comparator module 110. Thus, while the DAC 150 switches the states and converts the states to the second voltage VDAC, the comparator module 110 resets and gets ready for the next comparison.

[0022] During operation, in an example, the comparator module 1 10 is triggered by a clock signal ADC CLK to start operation. In an example, the ADC 101 includes a sample and hold circuit (not shown) configured to sample an analog signal, and generate the first voltage V[ _N in response to, for example, a rising edge of the clock signal ADC CLK. Further, the sample and hold circuit holds the voltage level of the first voltage VIN until a next rising edge of the ADC CLK. Further, the ADC 101 starts a conversion in response to the rising edge.

[0023] Specifically, in an example, the DAC 150 initiates the control signal to the circuit unit B9 to the enable state in response to the rising edge of the clock signal ADC_CLK. When the circuit unit B9 is enabled, the circuit unit B9 is initiated to the logic "1" state. In an example, because the other circuit units B8-B0 haven't been enabled, they are in a default state, such as a logic "0" state. In the example, the DAC 150 generates and settles the second voltage V _DAC corresponding to a binary sequence "1000000000".

[0024] Then, the comparator module 110 compares the first voltage Vi _N with the second voltage VDAC- In the Fig. 1 example, the first voltage VIN is higher than the second voltage VDAC, the comparator module 1 10 outputs a pulse (e.g., P9) in the second pulse output C _\ . In response to the pulse output, the reset control circuit 120 generates a reset signal, such as a rest pulse, and the like, to reset the circuits in the comparator module 1 10.

[0025] When the DAC 150 receives the pulse P9 in the second pulse output Ci, the circuit unit B9 maintains the state and passes the enable state to the circuit unit B8 in response to the pulse P9. When the circuit unit B8 is enabled, the circuit unit B8 is initiated to the logic "1" state. Because the other circuit units B7-B0 haven't been enabled, they are in the default state, such as logic "0" state. The DAC 150 settles the second voltage V _DA c corresponding to a binary sequence "1100000000".

[0026] The comparator module 1 10 then compares the first voltage VIN with the second voltage VDAC- In the Fig. 1 example, the first voltage Vm is lower than the second voltage VDAC the comparator module 110 outputs a pulse (e.g., P8) in the first pulse output C ₀ . In response to the pulse output, the reset control circuit 120 resets the circuits in the comparator module 1 10.

[0027] When the DAC 150 receives the pulse P8 in the first pulse output Co, the circuit unit B8 switches to the logic "0" state and passes the enable state to circuit unit B7 in response to the pulse P8.

[0028] The process can be repetitively executed to resolve the states of the circuit units B7-B0. After the circuit unit B0 finalizes its state based on pulse P0 for example, the DAC 150 outputs the digital value corresponding to the states of the circuit units B9 to B0, and may also output a done signal indicative of a finish of the conversion. [0029] According to an aspect of the disclosure, the operation of the ADC 101 does not require a high frequency clock signal, such as a clock signal having a frequency that is multiple times of the clock signal ADC CLK.

[0030] In an implementation of a related ADC, a comparator outputs a static output and an asynchronous clock signal having much higher frequency than the ADC_CLK. The static output is indicative of the comparison result, and the asynchronous clock signal provides timing information for the static output. In an example, the asynchronous clock signal has a rising edge with a delay to an output of the comparison result. The related ADC includes successive approximation registers (SAR) that operate based on the asynchronous clock signal to generate control signals for a DAC within the related ADC.

[0031] According to an aspect of the disclosure, the ADC 101 can be configured to have a faster speed than the related ADC. In an example, each bit of the ADC 101 is resolved in a bit cycle. The bit cycle includes the reset time and the comparator decision time. During the comparator decision time, the comparator module 1 10 compares the first voltage Vi _N with the second voltage VDAC, and outputs a pulse in one of the first and second pulse outputs based on the comparison. In an example, the comparison decision time may vary from bit to bit. During the comparator reset time, the comparator module 1 10 resets internal circuits to prepare for a next comparison. At the same time during the comparator rest time, the DAC 150 switches states based on the pulse in the first and second pulse outputs, and settles the second voltage VDAC accordingly.

[0032] For the related ADC, each bit cycle includes a comparator decision time, a delay between the static output and the asynchronous clock, a register delay, and a settling delay for the DAC within the related ADC. Because the sum of the delay between the static output and the asynchronous clock, the register delay, and the settling delay for the DAC is larger than the comparator reset time, in an example, the related ADC includes a delay circuit to introduce additional delay in the comparator reset time to match the sum. Thus, the bit cycle for the related ADC is longer than the bit cycle of the ADC 101. Thus, in an example, the clock signal ADC CLK's frequency can be increased.

[0033] According to another aspect of the disclosure, the ADC 101 has a reduced number of critical global routing signals than the related ADC. In the Fig. 1 example, the comparator module 1 10 passes two pulse output signals to the DAC 150. The control signals in the DAC 150 can be routed using local routing resources from one circuit unit to another circuit unit. In the related ADC example, the comparator outputs the static output and the asynchronous clock signal to the SAR registers of the related ADC, the SAR registers outputs multiple control signals, such as ten control signals for ten-bit DAC. The static output, the asynchronous clock signal, the control signals, the enable signal may require global routing resources. In addition, in an example, the delay circuit also generates an enable signal that needs to be globally routed.

[0034] According to another aspect of the disclosure, the ADC 101 consumes a reduced silicon area than the related ADC. In an example, the chain function in the DAC 150 is implemented using ten switches with three gates in each switch. The related ADC uses ten SAR registers to control the successive bits resolving, and consume more silicon area.

[0035] It is noted that, in the Fig. 1 example, the components of the ADC 101 are implemented on one IC chip. In another example, the components of the ADC 101 may be implemented on multiple chips, and are coupled together across the multiple chips.

[0036] Fig. 2 shows a diagram of a comparator module 210 according to an embodiment of the disclosure. In an example, the comparator module 210 is used in the ADC 101 as the comparator module 1 10. The comparator module 210 includes a comparator (COMP) 211, two cross-coupled NAND gates 212 and 213, two inverters 214 and 215, two NOR gates 221 and 222, and a NAND gate 223. These elements are coupled together as shown in Fig. 2.

[0037] In an embodiment, the comparator 21 1 receives a first voltage Vi _N and a second voltage VDAC, compares the first voltage and the second voltage, and generates a pulse in one of two outputs Oi and 0 ₂ based on the comparison. In an example, the two outputs Oi and 0 ₂ are reset to a relatively low voltage level before comparison. When the first voltage VIN is larger than the second voltage V _D AC, the comparator 211 outputs a positive pulse in the output 0 ₂ , and when the first voltage Vi _N is lower than the second voltage V _DA c, the comparator 21 1 outputs a positive pulse in the output O].

[0038] The cross-coupled NAND gates 212 and 213 and the inverters 214 and 215 form a latch to regenerate pulse outputs Co and Q . In an example, due to capacitive coupling, when one output has a real pulse, the other output has a false pulse. The real pulse is generally stronger than the false pulse. The latch passes the stronger pulse, and removes the weaker pulse, such that one and only one pulse output (Co or Ci) has a pulse. [0039] The two NOR gates 221 and 222 and the NAND gate 223 form a reset control circuit. The reset control circuit generates a reset signal COMP_RESET to trigger the comparator 21 1 to reset under various situations. In an example, when one of the pulse outputs Co or Ci has a pulse, the reset control circuit generates a pulse in the reset signal COMP_RESET to reset the circuits in the comparator 21 1. In another example, when an ADC clock signal, such as the clock signal ADC CLK in Fig. 1, has a rising edge, a signal ADC CLK RESET has a pulse, and then the reset control circuit generates a pulse in the reset signal COMP RESET to reset the circuits in the comparator 211. In another example, when the LSB bit has been resolved, a signal DONE RESET has a pulse in response to a finish of the ADC conversion, the reset control circuit generates a pulse in the reset signal COMP RESET to reset the circuits in the comparator 211.

[0040] Fig. 3 shows a timing diagram example 300 for an analog to digital conversion using the ADC 101 according to an embodiment of the disclosure. The diagram 300 includes a first curve 310 for the first voltage VIN, and a second curve 320 for the second voltage VDAC- The first voltage VI is sampled from an analog signal for conversion, and is held relatively stable during the conversion time. The second voltage V _D AC is output from the DAC 150 for example. The DAC 150 progressively resolves the bit values of a digital value corresponding to the first voltage Vi _N from the most significant bit (MSB), such as bit-9, to the least significant bit (LSB), such as bit-0, based on the comparison of the first voltage V _IN with the second voltage VDAC, and settles the second voltage VDAC based on the resolved bit values. As a result, the second voltage V _DA C varies and approaches the first voltage VIN gradually.

[0041] Specifically, in an example, during a time for resolving the state for the circuit unit B9, the circuit unit B9 is initiated to the logic "1" state, and the DAC 150 settles the second voltage VD _A C corresponding to a binary sequence "1000000000". Because the first voltage Vi _N is higher than the second voltage VDAC, the comparator module 110 outputs a pulse in the second pulse output Ci (e.g., P9 in Fig. 1). In response to the pulse output, the reset control circuit 120 resets the circuits in the comparator module 1 10. When the DAC 150 receives the pulse P9 in the second pulse output Q, the circuit unit B9 maintains the state and passes the enable state to the circuit unit B8 in response to the pulse P9.

[0042] Similarly, during a time for resolving the state for the circuit unit B8, the circuit unit B8 is initiated to the logic "1" state, and the DAC 150 settles the second voltage V _D AC corresponding to a binary sequence "1 100000000". Because the first voltage VIN is lower than the second voltage VDAC, the comparator module 110 outputs a pulse in the first pulse output Co (e.g., P8 in Fig. 1). In response to the pulse output, the reset control circuit 120 resets the circuits in the comparator module 110. When the DAC 150 receives the pulse P8 in the first pulse output Co, the circuit unit B8 switches to the logic "0" state and passes the enable state to circuit unit B7 in response to the pulse P8.

[0043] As shown in Fig. 3, each bit cycle includes a comparator reset time and a comparator decision time. During the comparator reset time, the circuit units in the DAC 150 switch logic states and the DAC 150 settles the second voltage VDAC accordingly.

[0044] Fig. 4 shows a flow chart outlining a process example 400 according to an embodiment of the disclosure. The process can be executed by the ADC 101. The process starts at S401 and proceeds to S410.

[0045] At S410, the ADC 101 is triggered by the clock signal ADC CLK. In an example, the ADC 101 starts operation in response to a rising edge of the clock signal

ADC CLK.

[0046] At S420, the ADC 101 performs an initial reset of the comparator module 110 and an initial settle of the DAC 150. For example, in response to the rising edge of the clock signal ADC_CLK, the reset control circuit 120 generates a reset pulse to reset the circuits in the comparator module 1 10, and the DAC 150 enables the circuit unit B9, and the circuit unit B9 enters an initial state, such as a logic "1" state. The other circuit units B8-B0 are not enabled and are in a default state, such as a logic "0" state. The DAC 150 settles the second voltage VDAC corresponding to the states of the circuit units B9-B0.

[0047] At S430, the comparator module 110 compares the first voltage V _M with the second voltage VDAC-

[0048] At S440, the comparator module 110 generates a pulse based on the comparison. For example, when the first voltage VI is higher than the second voltage V _D AC, the comparator module 110 generates a pulse in the second output signal Ci; and when the first voltage VIN is lower than the second voltage V _DA C, the comparator module 110 generates a pulse in the first output signal Co.

[0049] At S450, the comparator module 110 resets in response to the pulse, and the DAC 150 resolves a bit based on the pulse. For example, the reset control circuit 120 generates a reset signal to reset the circuits in the comparator module 1 10 in response to the pulse. The enabled circuit unit corresponding to the bit resolves its state based on the pulse. In an example, when the pulse is in the first output signal Co, the enabled circuit unit switches to a logic "0" state, and then enables a next circuit unit. When the pulse is in the second output signal Ci, the enabled circuit unit maintains the logic "1" state, and then enables a next circuit unit. When the next circuit unit is enabled, the next circuit unit enters a logic "1 " state in an example. Further, the DAC 150 settles the second voltage VDAC corresponding to the states of the circuit units B9-B0.

[0050] At S460, the ADC 101 determines whether the conversion is done. For example, when the circuit unit corresponding to the least significant bit (LSB) is resolved, the DAC 150 sets a DONE signal to logic " 1 " for example, to indicate that all the digital bits have been resolved, otherwise, the DONE signal is logic "0". When the conversion is done, the process proceeds to S470; otherwise, the process returns to S430 to resolve the next bit.

[0051] At S470, the ADC 101 outputs the digital bits based on the states of the circuit units B9-B0. The process then proceeds to S499 and terminates.

[0052] While aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples, alternatives, modifications, and variations to the examples may be made. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting. There are changes that may be made without departing from the scope of the claims set forth below.