Technical Field

This invention relates to a method and appar¬ atus for compensating for drift of the null point of a measuring device.

Background Art

The problem of compensating for drift of the null point of a measuring device arising from temperature change, component ageing or other effects is well-known. Such a null point drift is undesirable especially in the case of remote unattended installations where frequent manual adjustment cannot be made. It is known to com- pensate for drift by careful attention to design, use of high-grade low-drift components, and suitable inclu¬ sion of compensation components exhibiting complementary drift characteristics. However, such means of drift compensation are costly and achieve varying degrees of success due to component tolerances.

An arrangement for achieving drift compensation is described in U.S. Patent 4,043,412 in connection with a counting scale for providing a display of the weight and/or number of articles placed on the scale. The scale provides an analog electrical signal of the gross weight on the scale which is converted to a digital value by an analog to digital converter for processing in a micro¬ processor system. In order to compensate for drift, there is stored in the microprocessor system a number, which is periodically updated, related to the signal provided by the scale with no external load applied (i.e. in a null point condition). This number is combined, in certain modes of operation, with an averaged gross weight signal in order to compute a net weight value, which is employed to provide display information of the net weight and the number of articles on the scale.

Drift compensation is of particular importance in connection with signature verification devices com¬ prising a writing table transducer or signature pad (to which varying forces are applied as a person writes a signature) and a computer system for processing signals from the pad to provide a digital representation of a signature, which representation is compared with a specimen representation in order to validate the signa¬ ture. It is necessary to compensate for any drift of the signal from the pad in a null point condition of the pad in order to maintain an accurate zero reference.

Disclosure of the Invention

It is an object of the invention to provide an accurate, efficient and inexpensive means of compen- sation for drift of the null point of a measuring device, which is suitable for use with a signature verification device having a signature pad and a data processing means for collecting signals from the pad.

In accordance with one aspect, the invention provides apparatus for compensating for drift of the null point of a measuring device which provides an analog measurement output signal, the output of said measuring device being connected to data processing means via analog to digital converter means, character- ized by digital to analog converter means coupled to- said data processing means for converting a compensating value stored in said data processing means to an analog compensating signal, and comparison means for comparing said compensating signal with the measurement output signal from said measuring device to provide a comparison output signal representative of the difference between said measurement output and compensating signals, said analog to digital converter means being connected to re¬ ceive said comparison output signal to provide a digital equivalent thereof to said data processing means, and said data processing means being arranged, in order to

compute said compensating value, to store a value repre¬ senting the digital equivalent of a prior value of said comparison output signal with said measuring device in a null point condition and to compare this value with the digital equivalent of a current value of said com¬ parison output signal with said measuring device in a null point condition, and being arranged to modify said compensating value in dependence upon the result of the comparison between said previous and current values. In accordance with another aspect, the inven¬ tion provides a method for compensating for drift from a null point of a measuring device characterized by the steps of: a) comparing a measurement output signal from said measuring device when in a null point condition with a compensating signal; b) providing a comparison output signal representative of the difference between said measure¬ ment output signal and said compensating signal; c) comparing said comparison output signal with a previous value of the comparison output signal with the measuring device in a null point condition; d) modifying the compensating signal by a predetermined amount in the event of a given result of the comparison of step c); e) repeating steps a) to d) inclusive with successive modifications of said compensating signal until said comparison output signal attains a predeter¬ mined value; and f) employing said compensating signal to provide a comparison output signal to compensate for drift of the null point of the measuring device in sub¬ sequent use of the measuring device.

The apparatus for drift compensation in accord- ance with the invention employs a data processing means which will normally be present for collecting measurement signals from the measuring device. In addition the

apparatus is arranged to provide to the data processing means a signal which is already compensated for drift; hence it is unnecessary in contrast to the prior art arrangement described in U.S. Patent 4,043,412, for the data processing means to correct uncompensated signals by correction computations.

Brief Description of the Drawings

One embodiment of the invention will now be described by way of example with reference to the accom- panying drawings wherein:

Fig. 1 is a block diagram showing said embodi¬ ment; and

Figs. 2A-2F inclusive form a detailed flow diagram showing the operation of the apparatus shown in Fig. 1.

Best Mode for Carrying Out the Invention

Referring to Fig. 1, apparatus 10 for compen¬ sating for drift of the null point of a measuring device embodying the present invention is shown. In the illus- trated embodiment, the measuring device includes a writing table transducer or signature pad 12 which is utilized to generate a measurement output signal or wave¬ form representative of the varying forces applied by a person in writing predetermined data, such as a signature. A plurality of waveforms so generated, representing a corresponding plurality of signatures, are used to pro¬ duce a reference, which can then be utilized in veri¬ fication of the authenticity of the identity of the same person in the future by comparison of a similar sample with the reference. One suitable form of the table 12 is shown in United States Patent 4,143,357. The specific component types and values set forth herein for the various elements of the system are those used in the illustrated embodiment, but other appropriate types and values could be employed if desired.

OΛ1PI

An output signal e from the signature pad 12 is applied through a 10,000-ohm resistor 14 and a path 16 to the non-inverting input of a comparison means com¬ prising an operational amplifier 18, which may be a National Semiconductor type 308. The path 16 is connec¬ ted to a base reference potential, shown as ground, through a 1-megohm resistor 20.

The output of the amplifier 18 is connected over a path 22 to the input of an analog-to-digital converter 24 which may be of type ADC82AG manufactured by Burr-Brown Research Corporation. This is an eight- bit converter, which is connected for a 0 to +10v. input range. It is coupled to an input port 26 of a microcomputer 28, which may be an Intel SBC80/10, and controlled by the microcomputer via lines 29. An output port 30 of the microcomputer 28 is coupled to an eight-bit unipolar digital-to-analog converter 32 which may be a Precision Monolithics type DAC-03BD. The output of the converter 32 is connected through a 100,000-ohm fixed resistor 34 and a 100-ohm variable resistor 36 to a base reference potential, shown as ground. A further path extends from the slide of the variable resistor 36 through a 5,000-ohm variable resistor 38 and an 8,200-ohm fixed resistor 40 to the inverting input of operational amplifier 18. A 1-megohm fixed resistor 42 is connected in a path between the inverting input and the output of operational amplifier 18.

It may be seen that the analog voltage output of the digital-to-analog converter 32 is reduced in amplitude by the voltage divider comprising the resistor 34 and the trimmer potentiometer 36. This reduced voltage, designated as e , is applied as a compensating signal through the gain-setting resistors 38 and 40 to the inverting input of the amplifier 18, while the analog output voltage e of the signature pad 12 is applied to the non-inverting input of said amplifier.

OMPI

The analog output voltage E of the operation¬ al amplifier 18 is given approximately by

^E o ^=A < ^e s- ^e a> where A represents the amplification factor. For the resistor values cited above for resis¬ tors 38, 40 and 42, the amplification factor of the operational amplifier circuit is approximately 100.

From the above equation, it will be seen that the voltage E can be reduced to zero amplitude by suitable adjustment of the voltage ea, such that ea is approximately equal to e . Since the value of the voltage e is derived from the output of the digital- to-analog converter 32, which is controlled by the associated microcomputer 28 in a manner which will subsequently be described, means are thus provided for automatic correction of any drift of the voltage e away from the ideal value of zero which it should have when the pad is in the null condition with no writing pressure applied to said pad. The output voltage e _^ of the digital-to- analog converter 32 is reduced to a suitable level by the previously-mentioned voltage divider comprising the resistor 34 and the trimmer potentiometer 36. The set¬ ting of this potentiometer establishes the "step resolu- tion" value of the adjustment voltage e ; that is, the actual change in voltage ea which is produced by a single unit of incremental change in the digital value applied to the converter 32 by the microcomputer 28 through the output port 30. This setting represents a compromise between fineness of null adjustment and mag¬ nitude of the maximum drift of the signature pad 12 which can be corrected by the system, and thus sets a limit on the adjustment range.

The trimmer potentiometer 36 is initially adjusted such that E varies approximately four milli¬ volts for each incremental change of the digital data word applied to the input of the digital-to-analog

converter 32. For this adjustment setting, the maximum range of adjustment of E is slightly in excess of 1 volt as the digital data word which is applied by the microcomputer 28 through the output port 30 to the digital-to-analog converter 32 is varied from 0 to its maximum value which, for an eight-bit word, is 255 decimal or FF hexadecimal. Once this adjustment has been made, the input word to the digital-to-analog converter 32 is set by the microcomputer 28 to a mid- scale value of 128 decimal (80 hexadecimal). Next, with no force being applied to the signature pad 12, its output balance potentiometer 44 is adjusted to bring the amplifier output voltage E to a "null" value (i.e. 0 volts). At this time the voltage e is at an amplitude of about +5 millivolts, and the amplitude of the voltage ea_ is also at a value of approximately 5 millivolts. Now, by varying the value of the digital input word which is applied to the digital-to-analog converter 32, the output voltage E can be adjusted over a range of + or -.5 volt (500 millivolts) about the null point, so long as the voltage e is held constant at 5 millivolts.

The output voltage E of the operational amplifier 18 is converted to a digital value by the analog-to-digital converter 24 and is input to the microcomputer 28 through the input port 26. In this manner, the microcomputer 28, under appropriate software program control which will subsequently be described, can monitor the status of the null point and can correct for drift by modifying the value of the digital data word which is applied through the output port 30 to the digital-to-analog converter 32. The digital data word which is applied from the output port 30 to the con¬ verter 32 is latched or held in said port and contin- uously applied to the converter 32 until such time as a decision is made in the microcomputer that a change in value should be made in order to correct the drift.

( O. PI

As will subsequently be seen, a number of measurements are taken of the value Eo in order to obtain a number of data word values, from which an average is then taken and utilized during the sensing of a signature by the signature pad 12. As implemented in the signature verification system, the null drift of the signature pad 12 may be measured and corrected immediately prior to the making of each signature.

The method by which the microcomputer 28 functions to correct the null drift and to provide the desired compensating data word value is best explained by reference to the flow diagrams of Figs. 2A, 2B, 2C, 2D, 2E and 2F.

Referring now to Fig. 2A, the drift compensa- ting process is commenced at an appropriate time during overall signature verification system operation by the System Executive Program, as indicated by block 50. A loop counter COUNT is initialized to a value of 32; an initial value INITV is set to 16; and a totalizing counter SUM is cleared to 0 in starting the program, all as shown in block 52. These designated quantities may be stored in appropriate register or memory locations. A COUNT value of 32 is selected arbitrarily as a suitable total number of positive and negative loop samples from which an average may be derived, with each of the 32 iterations including both a positive and a negative loop sample, for a total of 64 samples. Other values than 32 would be suitable and can be selected. However, selection of a power of 2 simplifies the division procedure to be subsequently discussed, so that ideally COUNT should be selected from among the numbers 2, 4, 8, 16, 32, 64, etc. The division process which is used for derivation of an average can be conveniently accom¬ plished in the microcomputer of the illustrated example simply by shifting right the contents of a register an appropriate number of times.

The INITV value of 16 is selected to provide a suitable initial magnitude for the PRIOR VALUE parame- r

ter which is subsequently used in the program for evaluating each analog-to-digital data word generated. The totalizing counter SUM is set to 0 in preparation for accumulating a total which is used in establishing the average digital-to-analog data word value.

The process next proceeds to block 54, in which the PRIOR VALUE register is set to the INITV magnitude and the digital-to-analog control register, representing the data word value, is set equal to 0. It should be noted that these values could be retained in memory locations rather than in registers, if de¬ sired, at the expense of increased execution time. The microcomputer employed in the illustrated embodiment of the system contains a sufficient number of registers to permit the dedication of two of said registers for these parameters.

Continuing, as shown in block 56, the digital- to-analog data word held in the digital-to-analog control register is outputted to the digital-to-analog converter 32. It will be seen that block 56 is the first block in a loop 57 in which the digital-to-analog data word is successively incremented in value. For the first iteration of this loop 57, the digital-to- analog data word is 0, resulting in an analog voltage output of ea of 0 volts. This causes the output Eo. of the amplifier 18 to be set to some positive value of output voltage as determined by the previously-mentioned

Next in the process, the digital-to-analog data word is tested to determine whether or not it is at its maximum value of 255 decimal (FF hexadecimal), as shown in decision block 58. This maximum value condition cannot exist for a properly-adjusted and normally-functioning system, which has been initially set with the input word to a mid-scale value of 128 decimal, as previously described. However, in the event of certain malfunctions, such as excessive offset

O. PI

^' .- VV

voltage e from the signature pad 12 or a burnout failure of the digital-to-analog converter 32, the loop ^' 57 commencing with block 56 will be traversed 255 times without resulting in proper adjustment of the voltage ea. In such case, the "Yes" exit from the decision block 58 is taken; an error character, shown in the illustrated embodiment as the ASCII code "P", is stored in a re¬ served memory location, as represented by block 60; and path 62 is taken to an ABORT routine, represented by blocks 64 and 66 in Fig. 2F, in which a flag is set in block 64 to indicate that a hardware failure has occur¬ red. The ABORT condition may optionally be handled in a suitable manner by the Executive Program; for example, the host computer may be notified of the failure. It should be noted that this is a fatal or catastrophic failure mode and that attempts to utilize the system 10 must be prevented until the malfunction has been ser¬ viced. Storage of the unique error character "P" is useful in diagnostic analysis. Returning to Fig. 2A, and assuming that the data word test is successful so that the "No" exit from decision block 58 is taken, the analog-to-digital data output word representing the value of E is read into the microcomputer 12 from the analog-to-digital con- verter 24 through the input port 26, as represented by block 68 (Fig. 2B). The new analog-to-digital data word is then compared to the PRIOR VALUE, as indicated in decision block 70. Normally the new data word will be less than the PRIOR VALUE (or the initial value INITV for the first pass through the loop 57), because the voltage E will normally successively decrease as the digital-to-analog converter output is increased one step value for each pass through the loop 57.

If the new analog-to-digital data value is greater than the prior value, this indicates that some other factor is responsible, such as, for example, an increased force being improperly applied to the signa-

O.

ture pad 12 by a customer seeking to establish his or her identity. In such case, the "No" exit is taken from the decision block 70, and path 72 is followed to a routine comprising blocks 74, 76, 78 (Fig. 2F) , wherein an error indicator lamp may be flashed or an audible tone sounded until the fault clears or a time out occurs. The warning continues over loop 75 for so long as the system continues to determine, as shown by decision block 77, that the analog-to-digital data word is not less than the initial value INITV, or until some other limit has been reached in accordance with the programming of the system. Exit from the loop 75 occurs when it is determined in decision block 77 that the analog-to-digital data word is less than the initial value INITV. This will normally take place when the improperly-applied force is removed from the signature pad 12. In such case, the system returns via the "Yes" exit from block 77 over path 79 to block 52 (Fig. 2A) . If the system is operating normally, and the "Yes" exit from block 70 is taken, the PRIOR VALUE is replaced with the new analog-to-digital data value as shown in block 80. In addition to this, a small toler¬ ance factor must be added to the analog-to-digital data value stored at this time, because an AC ripple compo- nent may be present in the output voltage E of the amplifier 18. Addition of this tolerance factor is easily accomplished by incrementing the PRIOR VALUE register. Three such incrementing operations are carried out in the illustrated embodiment, though a different tolerance magnitude could be selected if desired.

Proceeding with system operation, in block 82 the analog-to-digital data word is tested, and if it is not equal to 0, the "No" exit is taken, and path 84 is followed to block 86, where the digital-to-analog data word held in the digital-to-analog control register is incremented one step, and operation continues from

block 86 over path 88 to the previously-mentioned block 56 for a further traverse of the loop 57. If the analog-to-digital data word is 0, the loop 57 is exited via the "Yes" exit of block 82. Next, in decision block 90, another diagnostic test is made to detect the instance in which either the circuitry of the signature pad 12 has failed or the power to the signature pad 12 has been interrupted. A test limit value LIMl is arbitrarily set relatively low (e.g. 10 decimal or 0A hexadecimal). In block 90, if the digital-to-analog data word is less than LIMl, the "Yes" exit is taken, the ASCII character for "L" is stored in the error character memory location, as indicated in block 92, and path 62 is followed to the ABORT routine. Here again, the error condition is fatal, and system operation must be suspended until maintenance is performed.

Next, assuming that the normal "No" exit is taken from decision block 90, the digital-to-analog data word held in the digital-to-analog control register is added to the totalized SUM being maintained in a register pair of the system microcomputer (specifically the H and L register pair in the illustrated embodi¬ ment), as shown in block 94 of Fig. 2C. In block 96, the digital-to-analog data word held in the digital-to-analog control register is set to the maximum value of 255 decimal (FF hexadecimal) prior to entering a second adjustment loop 98. This loop, which might be termed the N loop, controls the digital-to-analog converter such that the null point of the amplifier output voltage E is approached from the region in which E values are of negative polarity, in contrast to the first loop 57 described previously, which can be termed the P loop, wherein the null point is approached from the region in which E is of posi¬ tive polarity.

The use of the two loops 57 and 98 is based upon the results of experimentation, and the desire to

OΛIFI

enhance accuracy to the maximum possible extent. For a system in which a less rigorous standard of accuracy is ^' acceptable, the P loop only could be utilized. In fact, an operative system could be provided in which no averaging operation, such as will subsequently be described, takes place, and in which the data word value is determined simply by a series of operations of the P loop in which the output E is ultimately set by incrementation of the digital-to-analog register 32 to a value which results in a zero output voltage E when the signature pad 12 is at rest. In the illustrated embodiment however, the system incorporates both the P and N loops, and exhibits accuracy of a higher degree than that which could be obtained by using only one loop or by not performing the averaging operation.

The reason why greater accuracy is obtained by use of both the P and N loops is believed to be due largely to the asymmetrical ripple component present on the amplifier output voltage E . This ripple component arises from deliberate minimal filtering of the demodu¬ lator utilized in the force-to-voltage transducer circuitry of the signature pad 12 with which the present invention is utilized in the illustrated embodiment. The degree of filtering represents a design trade-off between dynamic response times of the transducer output voltage and the ripple amplitude. The asymmetry of the ripple waveform results from diode mismatch in the transducer demodulator, and its nature may be expected to differ from unit to unit. Thus, it is believed that incorporation of the P and N loops provides a means for attaining minimal error regardless of individual varia¬ tions in component values in the other portions of the system with which the present invention is utilized. Continuing now with the description of the system, in block 100 (Fig. 2C) the digital-to-analog data word is outputted to the digital-to-analog con¬ verter. Block 100 is the initial block in the N loop

_OΛ;PI_

98, and it will be seen that the digital-to-analog converter voltage during the operation of this loop commences at its maximum value and decreases incremen¬ tally in stairstep fashion until the loop exit decision condition is satisfied. It will be remembered from the previous discussion that exactly the opposite occurs in the P loop 57, in which the digital-to-analog converter voltage starts at 0 and increases toward its maximum value. Continuing with the process, in decision block

102, the digital-to-analog data word is tested for 0. If the data word is equal to 0, implying a circuit failure, the "Yes" exit from block 102 is taken, and ASCII character "N" (denoting the N loop 98) is stored in the error character memory location, as represented in block 104, and path 62 is followed to the ABORT routine, represented by blocks 64, 66 (Fig. 2F) .

Assuming that the normal "No" exit is taken from the decision block 102, the analog-to-digital data word is read as shown in block 106, and tested for 0 in decision block 108. In considering the operation of the N loop 98, it should be noted that since the signa¬ ture pad 12 of the illustrated embodiment produces a unipolar voltage waveform, the analog-to-digital converter 24 utilized therewith is of the positive polarity type. This converter translates all negative polarity voltage values to a 0 value digital word. Therefore, exit from the N loop 98 via the "No" exit of the decision block 108 takes place during the first iteration of the loop 98 in which the analog-to-digital data word output exceeds 0. Such iteration is the one during which the magnitude of the digital-to-analog data word has been decremented sufficiently that the corresponding voltage output ea applied to the invert- ing input of the amplifier 18 results in an output from said amplifier which is sufficient to produce an output from the analog-to-digital converter 24 of a value of 1

or more; that is, when the least significant bit of the word output from the analog-to-digital converter 24 becomes true (logical 1). For the eight-bit analog-to- digital converter used in the system of the illustrated embodiment, this occurs when output E slightly exceeds 39 millivolts.

For as long as the analog-to-digital data word remains 0, the "Yes" exit over path 110 from decision block 108 is taken, the digital-to-analog data word is decremented by one bit (thus decreasing the digital-to-analog converter output voltage by one step value) in block 112, and the program remains in the N loop 98, returning over path 114 to block 100. Once the analog-to-digital data word becomes non-zero, the "No" exit from block 108 is taken and the digital-to- analog data word is added to the SUM, block 116 (Fig. 2D) .

In block 118, the loop counter COUNT is decremented by 1 and is tested for 0 in decision block 120. The loop counter was originally initialized, as described previously, for a count of 32 decimal at the beginning of the operation.

By following path 122 from the "No" exit of block 120, it may be seen that the loop counter COUNT is counting the iterations of an outer loop 124 which encloses the P loop 57 and the N loop 98. For each pass through this outer loop 124, two values of the digital-to-analog data word are determined, one by the P loop 57 and one by the N loop 98. These values are then accumulated in the totalizer SUM. Therefore, for an outer loop count of 32, a total of 64 values are accumulated, necessitating division by 64 to obtain an average value for the digital-to-analog data word. This division is performed in blocks 126, 128 and 130 by six right shifts of the register pair (H and L in the illustrated embodiment) containing the SUM, as determined by the division count, or DCNT.

After the above division operation, the value SUM (now the average SUM) is compared with warning limits LIM2 and LIM3, in decision block 132 (Fig. 2E). If it is found that the value SUM is either greater than LIM2 or less than LIM3 an ASCII character "A" is stored for future diagnostic purposes, as shown by block 134, in the error character memory location, but system operation continues. Setting of these two ^' limits is somewhat arbitrary, and is dictated by the long-term aging drift characteristic of the circuitry. Typically, the limits might be set at the ten percent and ninety percent points of the digital-to-analog data word range. Hence, in the illustrated embodiment, suitable values are 225 decimal (El hexadecimal) for LIM2 and 25 decimal (19 hexadecimal) for LIM3.

If the value SUM passes the two limit tests of the block 132, the "No" exit is taken to block 136, where an ASCII SPACE (20 hexadecimal) character is stored in the error character memory location, to indi- cate an absence of error. It should be noted that this ASCII SPACE character, as well as all of the other error characters previously discussed, are of particu¬ lar significance only in the illustrated embodiment, and that other characters or codes may be alternatively used, as appropriate.

The operation then proceeds to block 138, in which the SUM value is loaded into the digital-to- analog control register, thereby becoming the digital- to-analog data word. In blocks 140, 142 and 144 (Fig. 2E), a final adjustment is made to the digital-to-analog data word. The null point or 0 voltage point of E , as read by the eight-bit analog-to-digital converter, is actually slightly less than 39 millivolts, corresponding to the converter's least-significant-bit resolution. The voltage E may be adjusted closer to the actual 0 than the analog-to-digital converter is capable of detecting,

( _ OAΈPI

by incrementing the digital-to-analog data word a suitable number of steps. It has been previously explained that the potentiometer 36 is initially adjusted such that the voltage E decreases approximately 4 millivolts for each increment (i.e. an increase of 1) of the digital-to-analog data word. A final adjustment of the voltage E is made in the loop comprised of blocks 142 and 144. It has been found by experience that an increment count DAJCT (or digital-to-analog adjustment count) of 8 gives good results in this respect. During extended system tests, the 0 adjustment has been consistently maintained within plus or minus 5 or 6 millivolts from true 0, which is less than a 1/4 bit error in respect to the resolution of the analog- to-digital converter in the illustrated embodiment.

As shown in Fig. 2F, the adjusted digital-to- analog data word is outputted to the digital-to-analog converter in block 146, a READY indicator is turned on in block 148, and return to the System Executive Program is effected, as shown in block 150.

Below is a group of program listings in Intel 8080 assembly language for the system operations des¬ cribed above.

ISIS 8080 MACRO ASSEMBLER, VI. 1 SIGNATURE PAD ADJUSTMENT SBR (PADCK. SRC)

TITLE 'SIGNATURE PAD ADJUSTMENT SBR (PADCK. SRC)'

; THIS SUBROUTINE CORRECTS THE DRIFT OF THE ZERO

OFFSET ; VOLTAGE OUTPUT OF THE SIGNATURE PAD CIRCUITRY...

; REFERENCED MEMORY LOCATIONS...

7ED9 LC EQU 7ED9H ; LED CONTROL WORD

7EDD TBLER EQU 7EDDH ; TABLE ERROR CHARACTER LOC.

; INPUT PORT ASSIGNMENTS...

0063 ADIN EQU 63H ; A/D DATA INPUT PORT

; OUTPUT PORT ASSIGNMENTS... 0062 DA EQU 62H ; D/A CONVERTER PORT 00E9 DISPL EQU 0E9H ; LED DISPLAY PORT

REFERENCED UTILITY SUBROUTINES,

0F94 DELAY EQU 0F94H 1-MILLISECOND DELAY 057A DLY250 EQU 057AH 250-MILLISECOND DELAY 0F6A SRDAH EQU 0F6AH SHIFT RIGHT DBL ARITH HL

; PROGRAM CONSTANTS,

0006 DCNT EQU 6 DIVISION COUNT

000A LIMl EQU 10D < 1 LSB TEST LIMIT

00E1 LIM2 EQU 225D UPPER RANGE LIMIT

0018 LIM3 EQU 25D-1 LOWER RANGE LIMIT

***********************************************

START OF ROUTINE...

5980 ORG 598JZTH

PADCK :

598 1E20 MVI E,20H LOAD LOOP COUNT 5982 210000 LXI H,0000 CLEAR SUM REGISTER

OLOOP:

5985 AF XRA A SET D/A OUTPUT TO 0 5986 2F CMA

5987 D362 OUT DA 5989 CD940F CALL DELAY ; WAIT FOR AMPLIFIER TO

SETTLE

598C 3A4B5A LDA INITV ; GET INITIAL VALUE 598F 57 MOV D,A ; PUT IT IN PRIOR-VALUE

REGISTER

^■ -

5990 3E50 MVI A,'P' LOAD ERROR CHARACTER 5992 32DD7E STA TBLER STORE IT 5995 01FF00 LXI B,00FFH INITIALIZE D/A DATA WORD AND CLEAR REGIS¬ TER B

PLOOP: 5998 0C INR INCREMENT D/A DATA WORD

5999 79 MOV A,C MOVE D/A DATA WORD FOR OUTPUT

599A 2F CMA COMPLEMENT FOR BUS INVERSION

599B D362 OUT DA OUTPUT TO D/A CONVER¬ TER 599D FEFF CPI 0FFH END OF RANGE IF DATA WORD IS MAX.

599F CA0E5A JZ ABORT 59A2 CD455A CALL INPUT GET NEW A/D DATA 59A5 BA CMP D IS IT < PRIOR VALUE? 59A6 D2175A JNC ERROR NO, PRESSURE'S ON

TABLE

59A9 57 MOV D,A SET PRIOR VALUE =

NEW VALUE

59AA 14 INR D ADD TOLERANCE 59AB 14 INR D AGAIN, 59AC 14 INR D AND AGAIN 59AD B7 ORA A A/D OUTPUT > 0? 59AE C29859 JNZ PLOOP YES, INCREASE D/A

OUTPUT 59B1 3E0A MVI A,LIMl TEST FOR < 1 LSB 59B3 B9 CMP C IS D/A DATA WORD

< LIMl?

59B4 D2115A JNC BAD YES , HARDWARE FAILURE? 59B7 09 DAD B SUM D/A DATA WORD

INITN :

59B8 3EFF MVI A,0FFH SET D/A OUTPUT TO FULL SCALE

59BA 2F CMA 59BB D362 OUT DA

59BD CD940F CALL DELAY WAIT FOR AMPLIFIER TO SETTLE

59C0 3E4E MVI A,'N' LOAD ERROR CHARACTER 59C2 32DD7E STA TBLER STORE IT 59C5 010000 LXI B,0000H INITIALIZE D/A DATA WORD AND CLEAR REGIS¬ TER B

NLOOP:

59C8 0D DCR C DECREMENT D/A DATA WORD

59C9 CA0E5A JZ ABORT FAILURE IF WORD GOES TO 0

59CC 79 MOV A,C MOVE FOR OUTPUT 59CD 2F CMA COMPLEMENT FOR DATA BUS INVERSION

59CE D362 OUT DA OUTPUT TO D/A CON¬ VERTER

59D0 CD455A CALL INPUT GET NEW A/D DATA 59D3 B7 ORA A SET STATUS FLAGS 59D4 CAC859 JZ NLOOP LOOP IF A/D DATA IS ZERO

59D7 09 DAD B SUM D/A DATA WORD 59D8 ID DCR E DECREMENT LOOP COUNT 59D9 C28559 JNZ OLOOP CONTINUE IF COUNT > 0

59DC 1E06 MVI E,DCNT ; LOAD DIVISION COUNT

DVD;

59DE CD6A0F CALL SRDAH ; SHIFT HL RIGHT ARITH¬ METIC

59E1 ID DCR E ; DECREMENT COUNT 59E2 C2DE59 JNZ DVD

_O.MPI

Λ

THE FOLLOWING SEGMENT TESTS THE D/A DATA WORD TO DETERMINE IF ITS VALUE FALLS BETWEEN THE LIMITS, LIM2 AND LIM3. IF SO, AN ASCII SPACE CHARACTER IS STORED IN THE 'TBLER' MEMORY LOCATION. IF ITS VALUE IS EITHER GREATER THAN LIM2 OR LESS THAN LIM3, THEN AN ASCII 'A' CHARACTER IS STORED IN 'TBLER' , MEANING THAT THE SIGNATURE PAD CIRCUITRY SHOULD BE ADJUSTED AT EARLIEST CONVENIENCE. THIS ERROR IS NON- FATAL, BUT IT DOES INDICATE THAT ATTENTION IS NECESSARY.

TEST:

59E5 2641 MVI H, 'A• ; LOAD ERROR CHR INTO H 59E7 3EE1 MVI A,LIM2 ; IS D/A DATA WORD > LIM2?

59E9 BD CMP L 59EA DAF559 JC STRCHR ; YES, IF CARRY 59ED 3E18 MVI A,LIM3 ; IS D/A DATA WORD < LIM3?

59EF BD CMP L 59F0 D2F559 JNC STRCHR ; YES, IF NO CARRY 59F3 2620 MVI H, ' ' ; NO, LOAD SPACE INTO H

STRCHR:

^• 59F5 7C MOV A,H ; COPY ERROR CHR TO

ACCUM.

59F6 32DD7E STA TBLER ; AND STORE IT

NEXT, THE OFFSET IS ADJUSTED TO APPROXIMATELY 0 BY INCREASING THE D/A OUTPUT A SPECIFIED NUM¬ BER OF STEPS...

59F9. 3A4A5A LDA DAJCT ; GET ADJUST COUNT

DOWN:

59FC 2C INR INCREMENT D/A CONTROL REGISTER

59FD 3D DCR A ; DECREMENT D/A ADJUST

COUNT ^•

59FE C2FC59 JNZ DOWN ; CONTINUE UNTIL COUNT

= 0

5 5A01 7D MOV A,L ; OUTPUT D/A DATA WORD 5A02 2F CMA 5A03 D362 OUT DA

EXIT1

5A05 3AD97E LDA LCW GET LED CONTROL WORD

10 5A08 E6DF ANI 0DFH TURN ON 'SIGN' LED 5A0A D3E9 OUT DISPL II II II II 5A0C AF XRA A CLEAR ACCUM. (ABORT FLAG)

5A0D C9 RET ; RETURN TO CALLING

15 ROUTINE

ABORT:

5A0E 3EFF MVI A,0FFH ; SET ABORT FLAG (IN

ACCUM.) 5A10 C9 RET ; AND RETURN TO CALLING

20 ROUTINE

BAD:

5A11 3E4C MVI A,'L' ; STORE ERROR CHARACTER 5A13 32DD7E STA TBLER 5A16 C9 RET ; RETURN TO CALLING

25 ROUTINE

ERROR:

5A17 AF XRA A SET D/A OUTPUT TO 0

5A18 2F CMA

5A19 D362 OUT DA

30 5A1B CD940F CALL DELAY WAIT FOR AMPLIFIER

TO SETTLE

5A1E 3A4B5A LDA INITV GET INITIAL VALUE

5A21 57 MOV D,A PUT IT IN PRIOR VALUE

ERR1

5A24 1E04 MVI E , 04H SET LOOP COUNT

ERR2:

5A26 7D MOV A,L PUT LCW IN ACCUM.

5A27 D3E9 OUT DISPL OUTPUT TO KEYPD LED'S

5A29 CD7A05 CALL DLY250 TIME OUT

5A2C EEFC XRI 0FCH REVERSE LCW BITS 2-7

5A2E 6F MOV L,A SAVE NEW LCW

5A2F CD455A CALL INPUT GET A/D DATA

5A32 BA CMP D < INIT. VALUE?

5A33 D2245A JNC ERR1 NO—LOOP

5A36 B7 ORA A SET STATUS FLAGS

5A37 CA245A JZ ERR1 RINGING IF A/D DATA

= 0

5A3A ID DCR E DECREMENT LOOP COUNT

5A3B C2265A JNZ ERR2 CONTINUE UNTIL COUNT

= 0 -

5A3E 3EFC MVI A,0FCH LOAD TURNOFF LCW

5A40 D3E9 OUT DISPL TURNOFF ALL LED'S

5A42 C38059 JMP PADCK GO RESTART THE ROUTINE

INPUT:

5A45 FB El ENABLE INTERRUPT

5A46 76 HLT WAIT FOR INTERRUPT

5A47 DB63 IN ADIN GET A/D DATA

5A49 C9 RET

; DATA AREAS... 5A4A 08 DAJCT: DB 08H D/A ADJUST COUNT 5A4B 0A INITV: DB 0AH INITIAL VALUE

5980 END PADCK ; RMW

ABORT 5A0E ADIN 0063 BAD 5All DA 0062 DAJCT 5A4A DCNT 0006 DELAY 0F94 DISPL 00E9 DLY25 057A DOWN 59FC DVD 59DE ERR1 5A24

ERR2 5A26 ERROR 5A17 EXIT1 5A05 INITN 59B8 INITV 5A4B INPUT 5A45 LCW 7ED9 LIMl 000A LIM2 00E1 LIM3 0018 NLOOP 59C8 OLOOP 5985 PADCK 5980 PLOOP 5998 SRDAH 0F6A STRCH 59F5 TBLER 7EDD TEST 59E5

ISIS 8080 MACRO ASSEMBLER, VI. 1

UTILITY SUBROUTINES REFERENCED BY PADCK. SRC

TITLE 'UTILITY SUBROUTINES REFERENCED BY PADCK. SRC

BRANCH TABLE ADDRESSES.

0F6A ORG 0F6AH

0F6A C39 06 JMP SRDAH

0F94 ORG 0F94H

0F94 C38605 JMP DELAY

; UTILITY SUBROUTINES

057A ORG 057AH

DLY250: 057A C5 PUSH B SAVE B&C REGIS¬ TERS 057B 06FA MVI B,250D LOAD LOOP COUNT

DLYLP: 057D CD8605 CALL DELAY CALL 1-MS DELAY SBR

0580 05 DCR B DECREMENT LOOP COUNT

0581 C27D05 JNZ DLYLP CONTINUE UNTIL COUNT = 0

0584 Cl POP B RESTORE B&C REGIS¬ TERS

0585 C9 RET DONE

DELAY:

0586 C5 PUSH B SAVE B&C REGIS¬ TERS

-BUREAU

OMPI

0587 0688 MVI B,136D ; LOAD LOOP COUNT

DLY1LP: 0589 05 DCR B ; DECREMENT LOOP COUNT

058A C28905 JNZ DLY1LP ; CONTINUE UNTIL COUNT = 0

058D Cl POP B ; RESTORE B&C REGIS¬ TERS

058E C9 RET ; DONE 069A ORG 069AH

SHIFT RIGHT DOUBLE ARITHMETIC REGISTER PAIR HL...

SRDAH:

069A F5 PUSH PSW 069B 7C MOV A,H 069C 07 RLC 069D IF RAR 069E IF RAR 069F 67 MOV H,A 06A0 7D MOV A,L 06A1 IF RAR 06A2 6F MOV L,A 06A3 Fl POP PSW 06A4 C9 RET

0000 END RMW

DELAY 0586 DLY1L 0589 DLY25 057A DLYLP 057D SRDAH 069A

It should be understood that the apparatus described above is efficient and inexpensive and pro- vides an accurate means for achieving drift compensation.