Title:
METHOD AND APPARATUS FOR CONNECTING VERTICALLY STACKED INTEGRATED CIRCUIT CHIPS
Document Type and Number:
WIPO Patent Application WO2003090256
Kind Code:
A3
Abstract:
Prepackaged chips (10), such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames (16) are removed including that portion which extends into the packaging. The bonding wires (20) are now exposed on the collective lateral surface of the stack (24). In those areas where no bonding wire (20) was connected to the lead frame (16), a bare insulative surface is left. A contact layer (26) is disposed on top of the stack (24) and vertical metallizations (40) defined on the stack (24) to connect the ends of the wires (20) to the contact layer (26) and hence to contact pads (34) on the top surface of the contact layer (26). The vertical metallizations (40) are arranged and configured to connect all commonly shared terminals of the chips (10), while the control and data input/output signals of each chip (10) are separately connected to metallizations, which are disposed in part on the bare insulative surface.
Inventors:
GANN KEITH D (US)
ALBERT DOUGLAS M (US)
ALBERT DOUGLAS M (US)
Application Number:
PCT/US2003/013569
Publication Date:
March 18, 2004
Filing Date:
April 22, 2003
Export Citation:
Assignee:
IRVINE SENSORS CORP (US)
GANN KEITH D (US)
ALBERT DOUGLAS M (US)
GANN KEITH D (US)
ALBERT DOUGLAS M (US)
International Classes:
H01L21/98; H01L25/10; (IPC1-7): H01L23/495; H01L21/48; H01L23/02; H01L23/28; H01L23/48; H01L23/52
Foreign References:
| US5281852A | 1994-01-25 | |||
| US5835988A | 1998-11-10 | |||
| US6172423B1 | 2001-01-09 | |||
| US6380624B1 | 2002-04-30 |
Other References:
See also references of EP 1497852A4
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