FIELD OF THE INVENTION

The present invention relates to the field of computer systems; particularly, the present invention relates to battery powered computer systems that remove power to subsystems and circuitry within the computer system during idle periods.

BACKGROUND OF THE INVENTION

Portable computers are common in the market today. These portable computers, often referred to as laptop and notebook computers, are often powered by batteries. Being that a battery only provides power for a specific duration (i.e., its battery life), efforts are currently being made to extend the battery life. In other words, for the same weight and performance of the computer system, efforts have been concentrated on maximizing the life of the computer system battery.

In typical computer systems, an operating system running on a processor in the system is responsible for handling basic tasks such as starting the system, handling interrupts, moving data to and from memory peripherals and managing the memory. Until recently, the operating system was disassociated from the mechanics of power savings. Similarly, application programs running on the operating system were also disassociated from power savings capabilities and functionality in the

computer system. However, some current operating systems have the capability to shut off portions of the computer system, such as specific peripherals. Application programs normally do not share this capability. Shutting off, or powering down, portions of the computer system results in the power savings.

In some computer systems, there are two types of application programs. Some application programs access hardware in the computer system through the operating system. In such a case, a call is made to the operating system which executes a task to complete the access to the hardware designated by the application program's call. On the other hand, some application programs access hardware in the computer system directly. These direct accesses pose a problem to operating systems that can shut down portions of the computer system. If the operating system turns off power to a specific subsystem or circuit that is to be needed or accessed by an application program, this functionality is no longer available to the application program. For instance, for an application program that accesses a sound subsystem, if the operating system powers down the sound subsystem, that application program is no longer able to access the sound subsystem. That is, the sound subsystem would not produce or receive sound(s) as dictated by the application program. Therefore, it is desirable to be able to turn off, or power down, a subsystem not being used in the computer system to save power while not removing or preventing its use when required by application programs.

Historically, application programs directly access the sound

subsystem hardware in the computer system. However, there are not many applications program that require use of the sound subsystem. Such application programs typically include entertainment and creativity software. Because there are only a few number of applications that directly access the sound subsystem, it would be desirable to power down the sound subsystem when not required in order to save power.

One of the problems that exists with powering down the sound subsystem is that a "clicking" or a "popping" sound occurs. This audible noise also occurs when powering up of the sound subsystem. This unwanted audible noise when repeated can become annoying to the user. Therefore, it is desirable to power down and power up a sound subsystem in a computer system without having to produce any unwanted audible noise.

The present invention provides a method and apparatus for controlling power to subsystems in the computer system. The present invention turns the subsystems on and off based on whether a particular subsystem is being accessed. In this manner, the present invention is able to place the computer system in a reduced power consumption state. In the case of portable computers and battery operated computers, the reduced power consumption results in extended battery life. The present invention is also able to power up and down the sound subsystem without producing audible noise.

SUMMARY OF THE INVENTION

A method and apparatus for controlling power to a subsystem in a computer system is described. The present invention includes a method and apparatus for enabling power to the subsystem in response to an access by an application program. The present invention also includes a method and apparatus for determining whether the subsystem is currently being powered. If so, the operating system of the present invention schedules a task to re-examine the subsystem after a predetermined period of time. Once the predetermined period of time elapsed, the operating system determines if the subsystem has been accessed during the time period. If the subsystem has not been accessed during the time period, then the operating system causes the subsystem to enter the reduced power consumption state. If the subsystem has been accessed, the operating system reschedules the task to check the subsystem again after another time period, thereby repeating the polling of the subsystem until no accesses to the subsystem occur and it may be placed into the reduced power consumption state.

The present invention also includes a control mechanism for controlling the subsystem. The control mechanism of the present invention includes a control state machine that generates signal(s) in response to detecting an access to the subsystem. A delay generator response to signals from the control state machine generates signals to cause the subsystem to enter the reduced power consumption state. The signals generated are sequenced such that a portion of the subsystem is powered

down prior to another portion.

In one embodiment, the delay generator of the present invention generates signals to amplifiers and integrated circuits in the sound subsystem of the computer system. The delay generator sequences the signals such that the amplifiers are muted prior to causing the integrated circuits to enter the reduced power consumption state. In this manner, the sound subsystem enters a state of reduced power consumption without producing an audible noise. Also the delay generator of the present invention sequences the signals when causing the sound subsystem to exit the reduced power consumption state so that an audible noise is not produced.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

Figure 1 is a block diagram of one embodiment of the computer system of the present invention.

Figure 2 illustrates one embodiment of the process of the present invention.

Figure 3A is a block diagram of one embodiment of the sound power control for powering up and powering down the sound subsystem of the present invention.

Figure 3B is a circuit schematic of one embodiment of the delay generator of the present invention.

Figure 3C is a timing diagram depicting the operation of one embodiment of the delay generator.

Figure 4 is a block diagram of another embodiment of the sound

power control for powering up and powering down the sound subsystem of the present invention.

Figure 5A is a circuit schematic of one embodiment of the sound power and clock sequencing logic of the present invention.

Figure 5B is a timing diagram of the operation of the present invention.

Figure 6A and B illustrates one embodiment of the process for powering down the sound subsystem according to the present invention.

Figure 7 is one embodiment of the process for powering up the sound subsystem according to the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

A method and apparatus for placing a computer system in a reduced power consumption is described. In the following detailed description numerous specific details are set forth, such as specific gates and logic, specific signal names, and specific register bit locations, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Also, well-known circuits have been shown in block diagram form, rather than in detail, in order to avoid unnecessarily obscuring the present invention.

Overview of the Computer System of the Present Invention

Referring to Figure 1 , an overview of a computer system of the present invention is shown in block diagram form. The present invention may be implemented on a general purpose microcomputer, such as one of the members of the Apple PowerBook™ family, one of the members of the IBM personal computer family, or one of several audio computer devices which are presently commercially available. Of course, the present invention may also be implemented on a multi-user system while encountering all of the costs, speed, and function advantages and disadvantages available with these machines. The preferred embodiment of the present invention is implemented on an Apple PowerBook™ computer system developed by the assignee of the present invention. As illustrated in Figure 1 , the computer system of the present

invention generally comprises a local bus or other communication means 100 for communicating information, a processor 103 coupled with local bus 100 for processing information, a random access memory (RAM) or other dynamic storage device 104 (commonly referred to as a main memory) coupled with local bus 100 for storing information and instructions for processor 103, and a read-only memory (ROM) or other non-volatile storage device 106 coupled with local bus 100 for storing non-volatile information and instructions for processor 103.

The computer system of the present invention also includes an input/output bus or other communication means 101 for communicating information in the computer system. A data storage device 107, such as a magnetic tape and disk drive, including its associated controller circuitry, is coupled with I/O bus 101 for storing information and instructions. A display device 121 , such as a cathode ray tube, liquid crystal display, etc., including its associated controller circuitry, is coupled to bus 101 for displaying information to the computer user, as well as a hard copy device 124, such as a plotter or printer, including its associated controller circuitry, for providing a visual representation of the computer images. Hard copy device 124 is coupled with processor 103, main memory 104, non-volatile memory 106 and mass storage device 107 through I/O bus 101 and bus translator/interface unit 140. A modem 108 and an ethemet local area network 109 are also coupled to I/O bus 101.

Bus interface unit 140 is coupled to local bus 100 and I/O bus 101 and acts a gateway between processor 103 and the I/O subsystem. Bus

interface unit 140 may also provide translation between signals being sent from units on one of the buses to units on the other bus to allow local bus 100 and I/O bus 101 to co-operate as a single bus.

An input/output (I/O) controller 130 is coupled to I/O bus 101 and controls access to certain I/O peripherals in the computer system. For instance, I/O controller 130 is coupled to controller device 132 that controls access to an alpha-numeric input device 122 including alpha-numeric and other keys, etc., for communicating information and command selections to processor 103, and a cursor control 123, such as a trackball, stylus, mouse, or trackpad, etc., for controlling cursor movement. The system also includes a sound subsystem 125 coupled to I/O controller 130 for providing audio recording and play back. Sound subsystem 125 may include a sound circuit and its driver which are used to generate various audio signals from the computer system and may further include a path through which the modem 108 can make sounds. I/O controller 130 may also provide access to a floppy disk and driver 126. The processor 103 controls I/O controller 130 with its peripherals by sending commands to I/O controller 130 through buses 100 and 101 , and bus interface unit 140.

Batteries or other power supply 152 may also be included to provide power necessary to run the various peripherals and integrated circuits in the computer system. Power supply 152 is typically a DC power source that provides a constant DC power to various units, particularly processor 103. Various units such as processor 103, display 121 , etc., also receive clocking signals to synchronize operations within the computer systems. These

clocking signals may be provided by a global clock generator or multiple clock generators, each dedicated to a portion of the computer system.

In the preferred embodiment, processor 103 is a 68000 brand processor, such as the 68040 processor manufactured by Motorola Corporation of Schaumberg, Illinois. The memory in the computer system is initialized to store the operating system as well as other programs, such as file directory routines and application programs, and data inputted from I/O controller 130. In the preferred embodiment, the operating system is stored in ROM 106, while RAM 104 is utilized as the internal memory for the computer system for accessing data and application programs. Processor 103 accesses memory in the computer system via an address bus within local bus 100. Commands in connection with the operation of memory in the computer system are also sent from the processor 103 to the memory using local bus 100. Local bus 100 also includes a bi-directional data bus to communicate data in response to the commands provided by processor 103 under the control of the operating system running on it.

Of course, certain implementations and uses of the present invention may neither require nor include all of the above components. For example, in certain implementations a keyboard or cursor control device for inputting information to the system may not be required. In other implementations, it may not be required to provide a display device displaying information. Furthermore, the computer system may include additional processing units, or buses 100 and 101 may be combined (collapsed into one bus) without the need for bus translator interface unit 140.

The present invention combines the use of hardware and software to provide an integrated power management scheme for the computer system. In the present invention, the power management scheme uses the operating system to monitor the activity of various subsystems within the computer system and controls powering down (and up) of particular subsystems. Some of the power management of the present invention may be controlled by firmware in microcontroller 132. In such a case, the firmware may be considered a subset of the entire operating system, although separate from the ROM and RAM based operating system.

Figure 2 illustrates the process of controlling power for a subsystem according to the present invention. Referring to Figure 2, initially, an application program generates an access to a particular subsystem, such as the sound subsystem 125 (processing block 201). Note that a subsystem, for purposes of the present invention, may include any number of peripherals and/or integrated circuits within the computer system, as well as logic and circuitry used to perform specific functions. Although the sound subsystem will be referred to with respect to the following discussion, the principles and scope of the present invention extends to other components within the computer system.

In response to the access, hardware in the computer system powers up the subsystem (processing block 202). This hardware is responsive to the application program. The application program causes the subsystem to be powered up in order to permit an access to that specific subsystem. For instance, if power has been removed from the sound subsystem, an

application program, upon attempting an access to the sound subsystem, causes hardware in the computer system to power up the sound subsystem and provide the functionality requested by the access of the application program.

After the application program powers up the subsystem to complete an access, the hardware provides an indication to the operating system that power is being applied to the subsystem (processing block 203). In the present invention, the application is not aware that its actions affect the power system. The application operates as if the power to the subsystem has always been on. In this way, the operating system is notified that the subsystem has been powered up again. This indication may be a signal initiated by hardware, such as by I/O controller 130, or may comprise one or more bits set, which the operating system or power manager in the computer system may later use to obtain the power status of the subsystem.

After the access has been completed by the application program (or even while it is being performed), the operating system detects whether a subsystem(s) is fully powered up (processing block 204). The operating system may detect the status of the various subsystems in the computer system in a real-time regularly scheduled task management system, wherein a specific task in the group of regularly scheduled tasks of the operating system is scheduled to determine whether certain subsystems are powered up. Note that because status is checked regularly, the operating system may detect the power up status while an application program is accessing the subsystem, as well as after the access has been completed.

Once the operating system has detected that the subsystem is powered up, the operating system designates a time period in the future at which it will reexamine the status of the subsystem (processing block 205). In one embodiment, the time period is fixed and begins with the starting of a fixed timer. For instance, if the operating system detects a particular subsystem is powered up, the operating system may schedule a task to occur fifteen seconds later to recheck the status of the subsystem.

At the expiration of the designated time period, a test determines whether the subsystem has been accessed since the last time the operating system checked the subsystem (processing block 206). If there has been an access since the last time the operating system has checked the subsystem, the processing continues at processing block 205, where processing block 205 and this portion of the process begins repeating. If the subsystem has not been accessed since the last time the operating system checked (e.g., the subsystem has been idle), the processing continues at processing block 207 where the operating system causes the subsystem to power down. The operating system causes the subsystem to be powered down by sending a command to a device or location in the computer system that regulates power to and from the subsystem. In the present invention, the operating system powers down the subsystem by removing its power and/or clock signal. The operating system may also cause one or more signals to be asserted, which are received as inputs and cause a device or subsystem with power down capabilities to power itself down. While the subsystem is in the powered down state, it is using a

reduced amount of power. In some cases, the subsystem may not be using power at all.

Besides powering down a subsystem, the operating system may also provide an indication, such as the setting of a register bit, that indicates the powered down status of the subsystem(s) to allow another task to determine the status of a subsystem (e.g., pass a message). In the preferred embodiment, a register bit is set by the operating system powering down the subsystem, or the application causing the subsystem to power up due to its access of it. Note also that the operating system can act as an "application", if one task or operating sub-program accesses the sound system, to be later detected by the power control monitoring task of the operating system.

At this point, the process continues at processing block 201 and continues to repeat the steps. The operating system continually checks the status of the subsystem to determine if there has been an access to the subsystem causing it to be powered up again. This may be performed by reading or receiving the indication set by the operating system. Therefore, the operating system uses a deferred polling mechanism to control the powering of subsystems in the computer system.

Currently Preferred Embodiment of the Present Invention

The currently preferred embodiment of the present invention provides for powering down the sound subsystem of a computer system through the use of software and hardware. The operating system of the present invention, in conjunction with hardware, causes the sound system to be

powered up or down according to whether the sound subsystem is idle or not (e.g., whether accesses have been made to that subsystem).

Figure 3A illustrates one embodiment of the sound power control hardware of the present invention. Referring to Figure 3A, I/O controller 130 includes a sound power control state machine 301 and a delay generator 302. The sound power control state machine 301 generates a sound power down signal 303 indicative of whether the sound subsystem is to be powered down. The sound power down signal 303 is received by delay generator 302, which provides a sound chip power down signal 305 to a power down input pin of the audio chip 309. Delay generator 302 also generates a mute signal 306 which is coupled to the gate of a p-channel transistor 307. Another output of the I/O controller 130 is a sound clock signal 304 generated by the sound power control state machine 301 of the present invention. The sound clock signal 304 is coupled to be received by a clock input of the audio chip 309.

The audio chip 309 of the present invention provides audio output comprising left and right channels to amplifiers 308. Amplifiers (amps) 308 are coupled as a driver to provide the audio data to speakers or headphones. Transistor 307 is coupled as a switch in series between power and amplifiers 308 and is used to power down amps 308.

The sound subsystem of the present invention is powered down using the sound chip power down signal 305 and mute signal 306. In the preferred embodiment, the sound chip power down signal 305 is active low, while the mute signal is active high. Audio chip 309 includes on-chip power

down capabilities responsive to signal 305 being low on its power down pin to cause itself to power down. On the other hand, mute signal 306 causes transistor to switch off and disable power to amps 308 when asserted high. Note that if audio chip 309 did not have its own power down capabilities, a similar switch (similar to transistor 307) could be used to disable power to the device. When the sound chip power down signal 305 and mute signal 306 are de-asserted, audio chip 309 and amps 308 return to full power.

The sound power control state machine 301 operates in cooperation with the operating system to power up and down the sound subsystem comprised of audio chip 309 and amps 308. The sound power control state machine 301 generates the sound power down signal 305 in response to a determination by the operating system that the sound subsystem has been idle (e.g., inactive) for at least a predetermined period of time. In one embodiment, this idleness of the subsystem is determined according to whether an access has been made to the sound subsystem during that predetermined period of time. The operating system may determine that an access has not occurred by reading one or more bit values stored in registers in the sound control state machine 301 that are indicative of the sound subsystem's status.

The sound power control state machine 301 includes a decoder (not shown) for monitoring all addresses sent on the address bus portion of bus 101 to determine, in a manner well-known in the art, if an address is within the address space of the subsystem. With respect to the sound subsystem, the decoder indicates when applications or an operating system (e.g.,

address mapping of the processor) access the address space mapped to the sound subsystem. When such an address has been received and decoded by the sound power control state machine 301 , an indication is provided (e.g., a register bit is set, a signal asserted, etc.).

To determine whether any particular access has occurred, the operating system examines the indication provided. If it is determined that power is currently being applied to the sound subsystem, the operating system, in a manner well-known in the art, schedules a task to be executed in a predetermined time in the future (e.g., starts a timer). During the task, the operating system returns to reexamine the state of the sound subsystem to determine if any other accesses to the sound subsystem have occurred in the intervening time period.

The time chosen to perform the check is a function of the typical time between accesses by a particular application program to a subsystem. In other words, the time set for returning to check the status is based on the time that typically occurs between accesses in order to avoid turning off power too soon or unnecessarily. In the case of the sound subsystem, the predetermined period of time is 15 seconds. If an access does not occur within that period, the present invention assumes that another access is not going to occur in the near future and that the subsystem may be placed in a reduced power consumption state. To implement the timing and scheduling necessary, the operating system may employ a hardware or a software timer. This timer may be closely associated, or operate in conjunction, with the global system timer or the clock received by the processor of the

computer system.

If an access has occurred during the intervening period, the operating system does not power down the subsystem. Instead, the operating system schedules another task to re-examine the sound subsystem again to see if an access has occurred during the next intervening period. If no access has occurred, the operating system determines that the sound subsystem is to be powered down.

When the operating system has determined that the sound subsystem should be powered down, the operating system causes the sound power control state machine 301 to assert the sound power down signal 303. In the currently preferred embodiment, the sound power down signal is active low. In response to the sound power down signal 303 being asserted, the delay generator 302 sequences the assertion of the mute signal 306 and the sound chip power down signal 305 to power down the sound subsystem without producing a "clicking" or a "popping" sound (e.g., an unwanted audible noise). In the present invention, the mute signal 306 is asserted prior to the sound chip power down signal 305. By asserting the mute signal 306 earlier, the amps 308 may be powered down prior to powering down audio chip 309, thereby eliminating any output of sound produced as a result of powering down (or powering up) the audio chip 309. In the present invention, the assertion of the sound chip power down signal 305 is delayed 10-20 milliseconds after the assertion of the mute signal 306.

To power down the subsystem, the mute signal 306 causes the

amplifier 308 to be powered down such that they are unable to provide the audio output to the speakers or the headphones. The sound chip power down signal 305 is received by a power down input pin of audio chip 309. In the present invention, audio chip 309 with its built-in power management responds to the assertion of a signal on its power down input pin, such that when the sound chip power down signal 305 is asserted (low), the audio chip 309 is placed in power down (e.g., a reduced power consumption state). Therefore, delay generator 302 provides the sequencing necessary to power down the audio subsystem comprised of the audio chip 309 and amplifiers 308. Note that although the amplifiers 308 are powered down by removing their power, there are other mechanisms to reduce power in the sound subsystem other than by removing the power of the amps 308, such as gating their inputs as shown in Figure 4 with field effect transistors (FETs) 402 and 403 or by using an amplifier with built-in power-down circuitry and an externally available power down signal.

The power savings that results from powering down audio chip 309 and amps 308 is attributable mainly to the powering down of audio chip 309. Although powering down amps 308 does provide some power savings, the main purpose behind powering it down is eliminate the unwanted audible noise that would couple through from audio chip 309 when it is powered down.

The sound power control state machine 301 and delay generator 302 are also responsible for powering up the sound subsystem when an access occurs (e.g., from an application program). When the decoder in the sound

power control state machine 301 determines that an access is being made to the sound subsystem (by comparing addresses), the sound power control state machine 301 deasserts the sound power down signal 303 to the delay generator 302. In response to the sound power down signal 303 being deasserted, the delay generator 302 sequences the de-assertion of both the mute signal 306 and the sound chip power down signal 305 to turn on the sound subsystem. Specifically, the delay generator 302 causes the mute signal 306 to be de-asserted 10-20 milliseconds prior to de-assertion of the sound chip power down signal 305. In this manner, the amps 308 are allowed to be fully powered up only after audio chip 309 has been powered up. By sequencing the signals, the powering up of the audio system does not ^" produce an unwanted audible noise. Note that although the delay used in the de-asserting the signals for powering up and asserting the signal for powering down the subsystem may be the same (except reversing the order of the signals), the present invention may use different delays depending on the differences between the speed at which the devices in the subsystems may be powered up or powered down. By using a delay generator that is programmable, design changes may still be made to audio circuitry even after the I/O controller has been "fixed", masked or designed.

It should be noted that the sound power control state machine 301 also produces the sound clock signal 304 to clock audio chip 309. When audio chip 309 is powered down, the sound clock signal 304 is disabled so that audio chip 309 only receives the clock signal held in the low state. Note that the sound clock signal 304 may be derived from an external clock

received by the sound power control state machine 301. Other embodiments may include the sound clock signal 304 being derived from clocking sources other than the sound power control state machine 301.

Figure 3A shows the delay generator 302 being internal to the I/O controller 130. However, the delay generator 302 may be separate external logic. Furthermore, the present invention may include two delay generators, one for powering up the sound subsystem and one for powering it down, each with its own delay time between the signals. In the currently preferred embodiment, the delay generator 302 comprises a programmable delay generator. Its programmable nature allows the sequencing delays to be set up late in the design cycle when the specification for the devices in the subsystems have been defined and any appreciable device specific qualities and limitations have been considered.

Figure 3B is a circuit schematic of one embodiment of the delay generator 302 of the present invention. Delay generator 302 is shown as two delay generators. Referring to Figure 3B, the two delay generators are shown receiving the sound powerdown signal 303 and a clock (or timebase) signal. One delay generator 321-326 is for the mute signal 306 delay; the other delay generator 331-336 is for the sound chip powerdown signal 305 delay. The clock signal may be the sound clock signal or the system clock signal. Multiple synchronous counter stages, shown as counters 321-326 and 331-336, are coupled in a cascaded configuration with the carry-out output from one counter being coupled to the carry-in input of the following counter, except for the carry-in input of counters 321

and 331 being coupled to the sound powerdown signal 303 and the carry- out output of counters 326 and 336 being coupled to logic gates 327 and 328, respectively. Each of the counters 321-326 and 331-336 is coupled to receive the clock signal. An OR gate 328 is coupled to receive the sound powerdown signal 303 and the output of the last counter (336) of one set of counters. An inverter gate 327 is also coupled to receive the carry-out output from the last counter 326 of the other set of counters. The sound powerdown signal 303 is also coupled to the clear (CLR) inputs of the counters 321-326, and coupled through inverter 330 to the set (SET) inputs of the counters 331-336.

The synchronous counter stages create the delays used in the present invention along with the chosen period of the clock or timebase driving them. Counter 325-|. _n or 335ι- _n represents one or more counters included to provide additional delay stages depending on the desired delays to sequence the signals. The operating system is still responsible for generating its own task delays (e.g., such as a 15 second polling delay).

The operation of the delay generator depicted in Figure 3B is shown in the timing diagram of Figure 3C. Referring to Figure 3C, while the sound powerdown signal 303 is low, the counters 321-326 are cleared as well as the carry-out output from the counter 326. Meanwhile, the counters 331-336 have had sufficient time to allow the low state of the sound powerdown signal 303 to propagate through them causing the CO output of counter 336 to be low. In this situation, the output of inverter gate 327 (the mute signal 306) is high and the output of OR gate 328 (the sound chip powerdown

signal 305) is low. Therefore, the audio chip 309 is powered down and the amplifiers 308 are muted. When the sound powerdown signal 303 goes to a high state, the output of OR gate 328 becomes high, causing the audio chip 309 to exit the powered down state. However, a delay is created by the state of the sound powerdown signal 303 propagating through the synchronous counter stages, therein causing the mute signal 306 to become low later. Note also that counters 331-336 have been SET by the inverted form of the sound powerdown signal 303 driving a low on their active low SET inputs, causing all CO outputs to go high. Later, when the sound powerdown signal 303 becomes low, all of the counter stages are cleared, such that the mute signal 306 becomes high immediately. Meanwhile, the high state of the sound powerdown signal 303 inverted at the set inputs of counters 331-336 allows these stages to propagate the non-inverted low state of sound powerdown signal 303 through to the OR gate 328, causing a delay of the sound chip powerdown signal 305 becoming low again to cause the audio chip 309 to enter the reduced power consumption state.

Figure 4 illustrates another embodiment of the sound power control of the present invention. Referring to Figure 4, the sound power control system includes sound power control state machine 301 within I/O controller 130 and delay generator 302 used to power down (and power up) the audio subsystem consisting of audio chip 309 and amps 308. Each of these components still provides the same functionality as described in conjunction with Figure 3. Note, however, that the delay generator 302 is shown as

external logic, and is not within the confines of I/O controller 130. In one embodiment, the delay generator 302 is a microcontroller which adds the flexibility of programmable delay through software control. Also note that a system clock signal 401 clocks the audio chip 309, instead of a clock signal generated by the sound power control state machine 301.

Furthermore, Figure 4 illustrates another mechanism for powering down or reducing power consumed by that of amplifiers 308 in the sound subsystem. Referring to Figure 4, the inputs to each of the amplifiers 308 are gated and turned off to provide the muting function. In this embodiment, p-channel transistors 402 and 403 are set in series between amplifiers 308 and the channel output from the audio chip 309. The sequencing described in conjunction with Figure 3 is still employed. When the mute signal 306 is asserted, the switches represented by transistors 402 and 403 are turned off, thereby preventing the sound output from reaching the amplifiers to mute the output.

Figure 5a illustrates one embodiment of sound power/clock sequencing logic of the sound power control state machine 301. Referring to Figure 5a, a sound flag signal 504 is coupled to an enable input of S-R flip-flop 501. The D input of flip-flop 501 is coupled to Vcc. A clear (CLR) input of flip-flop 501 is coupled to sound space access indication signal 505. The Q output of flip-flop 501 is coupled to the input of inverter 502. The output of inverter 502 represents the sound latch signal 508 that is output to a register and is also coupled to one input of NOR gate 503. The other input to NOR gate 503 is coupled to sound-on signal 506. The output

of NOR gate 503 is coupled to the D input of S-R flip-flop 511 and the input of inverter 507. The output of inverter 507 is the sound powerdown signal 509. The Q output of flip-flop 511 is coupled to the D input of S-R flip-flop 512. Both flip-flops 511 and 512 are coupled to receive the system clock signal 510. The system clock signal 510 is also coupled to one input of NOR gate 513. The other input to NOR gate 513 is coupled to the Q output of flip-flop 512. The output of NOR gate 513 is the sound clock signal 514.

The sound flag signal 504, sound-on signal 506 and the sound latch signal 508 represent accessible register bits. These register bits may be read from or written to according to the present invention. The operating system has access to the register bits, particularly to read status, as well as write specific bits of the registers. The operating system gains access to these bits by causing a read command to be issued by the processor over the system bus to the I/O controller 130. The operating system can deduce the state of the sound powerdown signal 509 by reading the states of the sound latch signal 508 and the sound on signal 506 through register 515.

The sound space access indication signal 505 is produced by the decoder 520 of the state machine (not shown to avoid obscuring the present invention). The sound space access indication signal 505 is asserted when an applications or operating system access to the sound space occurs through the 68K processor. This causes the Q output to be a logical zero. The Q output being low causes the output of inverter 502 to be high, thereby causing the sound latch signal 508 to be asserted (e.g., high) to indicate that an access occurred to the sound space. The output of inverter 502

being high also causes the output of NOR gate 503 to be low. When the output of NOR gate 503 is low, the output of inverter 507 is high, such that the sound power down signal 509 is de-asserted (or remains de-asserted). In such a case, the audio chip 309 in the sound subsystem coupled to the signal on its power down input is not placed in a power down mode. As for the sound clock signal 514, when the output of NOR gate 503 goes low, flip- flops 511 and 512 operate as dual rank synchronous gating logic to provide the sound clock signal 514 through NOR gate 513 (without creating the hazards of "runt" pulses).

Figures 6A, 6B and 7 illustrate the currently preferred process for turning off of the sound subsystem and, subsequently, turning on of the sound subsystem, respectively, using of the sound power/clock sequencing logic of Figure 5a. Figure 5b will be discussed later.

Referring to Figures 6A and 6B, the software and hardware sequences, respectively, for turning on and off the sound is shown, wherein a determination is made by the operating system as to whether the sound subsystem is idle, and if so, the operating system powers down the subsystem. The process begins when the operating system checks the sound latch signal 508 (processing block 601). The operating system performs the check by reading the register value of the sound latch signal 508 to determine whether the sound subsystem has had an access since the last time the operating system had checked. At processing block 602a, a test determines if the sound latch signal 508 is high. If the sound latch signal 508 is not high, processing continues at processing block 602b

where the operating system performs other tasks assigned, in a manner well-known in the art, and schedules another time when the operating system is to re-examine the powered state of peripherals in the system, thereby repeating the process. Note that the operating system does not have to repeatedly check the powered state of peripherals in the system immediately because the hardware in the computer system acts immediately to power up the sound subsystem when the sound latch signal 508 goes active (as soon as the sound powerdown signal 303 goes high) and follows processing blocks 602c, 611 and 612 in Figure 6b waiting at processing block 613 until the operating system proceeds from processing blocks 603 through 607 of Figure 6a. Thus, prior to processing blocks 603- 606 being performed, the hardware has completed processing blocks 611 and 612 and is waiting at processing block 613 until operating system software clears the sound-on signal 506 at processing block 607, which will cause the sound powerdown signal 303 to become low.

If the sound latch signal 508 is high at step 602a, the hardware flow continues at processing block 611 (Figure 6B), where the hardware starts a timer to allow for power-up stabilization of the audio chip 309. Note that the sound latch signal 508 being high at processing block 602a is reflected in the sound powerdown signal 303 checked at processing block 602c in hardware. When the hardware delay timer has expired, the hardware next performs processing block 612 to remove the mute on the amplifiers. The operating system proceeds to processing block 603 from processing block 602a by setting the sound-on signal 506 high at processing block 603,

unaware of when hardware performed processing blocks 602c, 611 , 612 and 613. The output of NOR gate 503 remains low, causing the sound powerdown signal 303 to remain high and the sound clock signal 514 to continue.

The operating system also clears the sound latch signal 508 (processing block 604). With reference to Figure 5A, the sound latch signal 508 is cleared by pulsing the sound flag signal 504 high and then low. The pulsing of the sound flag signal 504 is accomplished by the operating system performing two write operations to the register, first to set the bit high and the second to set it low. However, since the sound-on signal 506 is high, only the sound latch signal 508 will change state. In another embodiment, a pulse generator circuit within the I/O controller may be included to reduce these two operations (processing blocks 603 and 604) into one operation.

Next, the operating system waits for a predetermined time period to recheck the status of the sound subsystem. In other words, the operating system schedules a task to re-examine the status of the sound latch signal 508 after the expiration of the predetermined time period, later returning to processing block 606. In the currently preferred embodiment, the operating system waits approximately 15 seconds at which time the operating system again checks the state of the sound latch signal 508 (processing block 605).

A test determines if the sound latch signal 508 is high at processing block 606. If the sound latch signal 508 is high, processing continues at processing block 603, where the sound latch signal 508 is cleared and the

sound-on signal 506 is redundantly forced high and the portion of the process at block 603 begins repeating. However, if the sound latch signal 508 is not high, indicating that there has been no access of the sound subsystem in the intervening period, the operating system processing continues at block 607, where the sound-on signal 506 is cleared. This causes the D input of flip-flop 511 in Figure 5A to go high and result in the sound clock signal 514 to stop low in two system clock cycles. More importantly, the clearing of sound on signal 506 here causes sound powerdown signal 303 to go low (since sound latch signal 508 was already low), prompting the hardware delay generator to function at processing block 614 in Figure 6B. The hardware causes the delay generator to mute the headphone and speaker amplifiers at processing block 614 and the delays the turn-off of the audio chip in processing block 615 until after the predefined delay. The delay generator provides a delay of approximately ten milliseconds for settling time before asserting the sound chip powerdown signal 305 in processing block 615. The hardware will wait at processing block 602c while the operating system returns to processing blocks 601 , 602a, and 602b.

In sum, processing blocks 602c, 611 and 612 represent the process of turning on the sound power, processing blocks 603-606 represent the process of maintaining the sound power, processing blocks 607 and 614- 615 represent the process of turning off sound power and processing blocks 601 , 602a-c represent the process of waiting for a sound space access.

Referring to Figure 7, the software/hardware sequence for turning on

the sound subsystem (assuming the sound is off) is shown as an overview. If the sound system is already on, an access causes no change to the sound clock signal 514 and the sound powerdown signal 303. Referring to Figure 7, the process begins by an application program accessing the sound address space (processing block 701), such as, for instance, through a write operation. Assuming that the sound was off, this access causes the sound space access indication signal 505 to be asserted low, and therefore causes the sound latch signal 508 to go high (processing block 702). When this sound space access indication signal 505 is asserted, the sound powerdown signal is de-asserted (processing block 703) and the sound clock signal 514 begins clocking (processing block 704) without hazards. In response to the sound powerdown signal 303 being high, the delay generator de-asserts the sound chip powerdown signal 305 immediately to cause audio chip 309 to exit the reduced power consumption state. The delay generator at processing block 705 also delays 10 milliseconds before enabling power to the speaker and headphone amplifiers, or before reenabiing their inputs (processing block 706). In this manner, the unwanted audible noise is avoided.

Note that the delay generator may avoid asserting the sound powerdown signal 305 low if the application program accessed sound space directly, right after the operating system turned off the sound-on signal 506. In the present invention, if the sound powerdown signal 303 is low for less than the 10 millisecond delay period of the power down sequence, then the delay generator turns amps 308 back on (or stops

muting the amplifiers by driving mute signal 306 back low) after 10 more milliseconds of delay since the mute signal 306 would go high (causing muting) at the first sign of the sound powerdown signal 303 going low. This is illustrated in the timing diagram in Figure 5B, which depicts a sound access (shown in effect by sound latch signal 508) that occurs immediately following the operating system clearing the sound-on signal 506. The dotted line B shows the extra time that the sound powerdown signal 303 must be in the low state to cause the sound chip powerdown signal 305 to become low. The dotted line C shows the transition to the low state that would have occurred to the sound chip powerdown signal 305 if the sound powerdown signal 303 would have been in the low state long enough. Note that the transition from low to high (A) of the sound-on signal 506 illustrates where the operating system check (at processing block 602a) detected sound latch signal 508 high, and causes processing to continue at processing block 603 where the sound-on signal is set.

The register bits used in the sound power control and sequencing logic may include bits to mask other bits used in the power control. In this manner, the system can be configured to allow only certain "subsystem aware" applications to control the powering on of the hardware. For instance, an application or master may be allowed to control or prevent modem sound, where a modem in the system might attempt to turn on the sound to reflect the tones coming up through the phone. Likewise, the operating system may be subjected to control through the use of masking bits. For instance, if a particular bit is set, the operating system at times may

not be allowed to turn off the subsystem, if a "subsystem aware" music or speech application desires to keep sound subsystem performance and responsiveness as high as possible by preventing operating system intervention.

The present invention may be applicable to other computer system components. For instance, the present invention could be used with a modem or LAN, where application accesses are infrequent enough, such that their detection may be used as criteria of enabling.

The sequencing of present invention may also by used when attaching another monitor to a computer system already having a monitor, such as when an external monitor is attached to a portable computer with an LCD display. The LCD screens that are built into the portable computer typically require the sequencing of a blanking signal and the power to be supplied to the screen. In such a case where an external monitor is hooked up to the system, a peripheral controller incorporating the teachings of the present invention may be capable of turning off the LCD screen while the user uses the external screen. The delay generator can be programmed to ensure that at least one of the screens is always clear while power is supplied or taken away from the other monitor and so that power, blank signals and information carrying signals, such as clocks and data, are sequenced according to the manufacturers specifications, so that proper operation occurs. This basically allows a plug-and-play system to be implemented. By only having to have one of the screens powered, the system incurs a power savings. Note also that this occurs while the

machine is turned on, such that no sleep docking or changing of the hardware configuration in the sleep mode is required. The user could indicate their screen choice through software control (e.g., menu selection) or by closing the LCD clamshell/connection of external monitor or other protocol. In this example, a user access in the form of, for instance, the opening or closing of clamshell may be detected to initiate the sequencing of signals (such as blanking data) and power with a delay generator, and perhaps initiating other hardware activity, such as re-mapping display buffers, if necessary.

Thus, the present invention turns the subsystems on and off based on whether a particular subsystem is being accessed. In this manner, the present invention is able to place the computer system in a reduced power consumption state. In the case of portable computers and battery operated computers, the reduced power consumption results in extended battery life. The present invention is also able to power up and down the sound subsystem without producing audible noise.

Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that the particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of the preferred embodiment are not intended to limit the scope of the claims which in themselves recite only those features regarded as essential to the invention.

Thus, a method and apparatus for controlling power to subsystems of a computer system has been described.