PRIORITY DOCUMENTS

[0001] The present application claims priority from Australian Provisional Patent Application No. AU2012901 143 titled "METHOD AND APPARATUS FOR DISPLAYING A 1 BIT PER PIXEL IMAGE ON A TFT LCD" and filed on 21 March 2012; the entire content of which is hereby incorporated by reference.

TECHNICAL FIELD

[0002] The present invention relates to Liquid Crystal Displays (LCDs). In a particular form the present invention relates to methods and apparatus for displaying an image using a TFT LCD.

BACKGROUND

[0003] Low cost or low end products with graphical LCD type displays typically use monochrome (ie 1 bit per pixel or lbpp) Super Twisted Nematic (STN) LCDs. STN LCDs are passive matrix devices, and are cheap, consume low power, do not require backlights (and thus can be read in direct sunlight), and importantly can be driven by low cost/low power microprocessors. This aids use in a wide range of low cost devices such as displays in lighting controllers used in building automation systems, and portable or hand held devices such as calculators, portable testing devices etc. However whilst STN LCDs are cheap and simple to drive making them suitable for use in low cost electronic devices, they typically have poor contrast and slow response times, especially as the number of pixels is increased.

[0004] More recently colour Thin Film Transistor (TFT) LCDs have been developed. TFT LCDs are active matrix devices (one transistor per pixel) and offer vastly superior contrast, response time, and viewing angles compared to older passive matrix STN LCDs. Whilst the cost of such devices has been dropping, making them more feasible to include in low end electronic products, the low cost/low power microprocessors typically used in such low end devices typically have insufficient resources and processing power to drive a colour TFT LCD.

[0005] In particular colour TFT LCD's typically require a minimum of 16 bits of data to be transferred per pixel whereas STN LCD only require 1 bit per pixel. Transferring such large amounts of data generally requires a parallel interface, however low cost microprocessors do not usually have a native parallel bus interface suitable for connection to the LCD controller, meaning the connection must be implemented using general purpose Input Output (IO) pins of the processor. Whilst this is possible, transferring the data this way consumes a large amount of processing time, resulting in a slow update rate on the display and also leaving the processor little time to perform any other tasks. In addition, the 1 bit per pixel image would normally by stored as 8 pixels per byte (in order to reduce the amount of memory required to store the image), meaning that additional processing is required to unpack the data before transferring it via the parallel interface. All of these factors add up to make it very difficult to use colour TFT LCDs and achieve good performance while still using a low cost microprocessor.

[0006] There is thus a need to provide an apparatus for displaying an image on a TFT LCD driven by a low cost microprocessor.

SUMMARY

[0007] According to a first aspect, there is provided an apparatus for displaying a 1 bit per pixel image on a TFT LCD, the apparatus comprising:

a microprocessor comprising a memory for storing a 1 bit per pixel image;

a serial interface for sending the 1 bit per pixel image as a serial data stream in which each pixel is represented as either a low data bit value or a high data bit value;

a multiplexer for receiving the serial data stream from the serial interface and mapping each serial data bit in the serial data stream to a n-bit parallel data value for sending to a TFT LCD module, wherein each low data bit in the serial data stream is mapped to a first n-bit parallel data value, and each high data bit in the serial data stream is mapped to a second parallel n-bit data value; and

a TFT LCD module comprising a TFT LCD, the TFT LCD module configured to receive the parallel data stream from the multiplexer and display as an n-bit per pixel image on the TFT LCD.

[0008] In a further aspect the multiplexer receives the first n-bit parallel data value and the second n-bit parallel data value via at least one input port. In a further aspect multiplexer receives the first n-bit parallel data value on a first input port, and the second n-bit parallel data value on a second input port. In a further aspect the multiplexer is preconfigured with the first n-bit parallel data value and the second n- bit parallel data value. In a further aspect the first n-bit parallel data value corresponds to white and the second n-bit parallel data value corresponds to black. In a further aspect the value of n is a power of 2 and in yet a further aspect the value of n is 16.

[0009] In a further aspect the apparatus comprises a Direct Memory Access (DMA) controller for transferring the 1 bit per pixel image from the microprocessor to the TFT LCD module via the multiplexer. In a further aspect the TFT LCD module comprises a LCD controller comprising a receiver configured to receive the parallel data stream from the multiplexer.

[0010] According to a second aspect, there is provided a method for transferring a 1 bit per pixel image to an n bit per pixel image for display by a TFT LCD, the method comprising: sending a 1 bit per pixel image from a microprocessor as a serial data stream to a multiplexer in which each pixel is represented as either a low data bit value or a high data bit value;

mapping the serial data steam to a n-bit parallel data stream in the multiplexer, wherein each serial data bit in the serial data stream is mapped to a n-bit parallel data value wherein each low data bit in the serial data stream is mapped to a first n-bit parallel data value, and each high data bit in the serial data stream is mapped to a second parallel n-bit data value;

sending the n-bit parallel data stream to a TFT LCD module comprising a TFT LCD; and displaying the received n-bit parallel data stream as n-bit per pixel image in the TFT LCD.

[001 1] In a further aspect the method comprises receiving on at least one input port the first n-bit parallel data value and the second n-bit parallel data by the multiplexer. In a further aspect the first n-bit parallel data value is received on a first input port, and the second n-bit parallel data value is received on a second input port. In a further aspect the method comprises pre-configuring the multiplexer with the first n-bit parallel data value and the second n-bit parallel data value. In a further aspect the first n-bit parallel data value corresponds to white and the second n-bit parallel data value corresponds to black. In a further aspect the value of n is a power of 2 and in yet a further aspect the value of n is 16.

[0012] In a further aspect the method comprises transferring the 1 bit per pixel image from the microprocessor to the TFT LCD module via the multiplexer using a DMA protocol.

BRIEF DESCRIPTION OF DRAWINGS

[0013] An illustrative embodiment will be discussed with reference to the accompanying drawings wherein:

[0014] FIGURE 1 is a block diagram of an apparatus for displaying an n-bit per pixel image on a TFT LCD;

[0015] FIGURE 2 is a flowchart of a method for transferring a 1 bit per pixel image to an n bit per pixel image for display by a TFT LCD; and

[0016] FIGURE 3 is a circuit diagram of an embodiment for displaying a 16-bit per pixel image on a TFT LCD.

DESCRIPTION OF EMBODIMENTS

[0017] Referring now to Figure 1, there is shown a block diagram of an embodiment of an apparatus 100 for displaying an n-bit per pixel image 104 on a TFT LCD module 150 comprising a TFT LCD 156. Typically n will be 8 or 16 (ie an 8 or 16 bit per pixel image), although it may be any power of 2 (eg 2, 4, 8, 16, 32, 64...) depending upon the requirements or capabilities of the TFT LCD module used. In the embodiment shown in Figure 1 the TFT LCD 156 is a colour display, although in other embodiments it could be n-bit per pixel grey scale module. In the embodiment shown in Figure 1 the TFT LCD module 150 comprises a TFT LCD 156, and an associated LCD controller 151 with memory 152. In this embodiment the memory 152 is integrated in the LCD controller but in other embodiments it may be a separate component operatively coupled to the LCD controller 151 or LCD module 150. In this embodiment the n-bit image data is transferred to the LCD controller 151 which is then responsible for actually transferring that image to the LCD 156 for subsequent display.

[0018] The apparatus 100 comprises a microprocessor 110 (also referred to as a microcontroller), and a memory 11 1 , which can be integrated with the microprocessor 110, or provided as a separate component operatively connected or coupled to the microprocessor 1 10. A 1 bit per pixel (ie monochrome) image (shown as representation 102) is stored in a portion 112 of the memory 11 1. In the example embodiment shown in Figure 1 the memory 1 12 corresponds to a contiguous set of memory addresses but another set of non-contiguous memory addresses could be used. This 1 bit per pixel image 102 is suitable for display by a STN LCD. Each pixel is either a low (eg 0) value (or data bit) or a high (eg 1) value (or data bit) and an appropriate value (eg 1 or 0) 1 16 is stored in the memory 1 1 1. Typically a low value corresponds to an off pixel and thus has the background colour (typically light grey on a STN LCD, but it could be white or some other colour) and a high value corresponds to an on pixel (typically black in a STN LCD, but again it could be some other colour). For example in representation 102 low pixels are light grey and high pixels are black. Of course the reverse arrangement could also be used (ie low =on/black, high = off/light grey). In order to reduce the amount of memory required to store the image, the memory will typically pack or compress the data in the memory, for example by using a single byte 1 18 to store 8 pixels (ie 8 bits) of data (see Figure 1).

[0019] The microprocessor further comprises a serial interface 1 14 which is used for sending the 1 bit per pixel image as a serial data stream 120. Most low cost microprocessors either lack native parallel data interfaces, or their use to transfer an image would consume a large amount of processing time, resulting in a slow update rate on the display and also leaving the processor little time to perform any other tasks (eg the tasks the microprocessor / device / product is primarily designed to perform). In this embodiment the serial interface 1 14 is a serial peripheral interface bus (SPI) which is a synchronous serial data link standard that is capable of operating in full duplex mode, and which is typically available on most low cost microprocessors. Communication using SPI uses a master/slave mode in which the master device initiates transmission of a data frame. In this case the microprocessor 110 is the master and the multiplexer 130 is the slave device with the data frame being the image. The 1 bit per pixel image is then sent as a serial data stream 120 in which each pixel is represented as either a low data bit value (ie 0) or a high data bit value (ie 1), with one bit being transferred each clock cycle. A clock signal (CLK) is sent from the SPI on port 121 to synchronise the microprocessor and TFT LCD module 150. It drives the write latch on the LCD controller to latch a 16 bit value from the output of the multiplexer into the LCD controller's memory for every bit of the serial data stream.

[0020] Further as 8 pixels are typically packed into a single byte 1 18 in memory 1 1 1 , the use of the serial interface with the multiplexer avoids the further processing time that would be required to unpack the data before transferring it over a native parallel interface if it was provided. Instead the use of the hardware serial interface eliminates the need for the microprocessor to unpack the data, and allows 8 bits of data to be transferred at a time to the display with only minimal processor intervention or overhead. In this case the CPU needs only feed each byte 118 to the serial port which is a much faster operation than having to unpack the data.

[0021] As the TFT LCD module 150 requires a parallel input, a multiplexer 130 is used to receive the serial data stream 120 from the serial interface 114 on input SEL. The multiplexer then maps each incoming serial data bit in the serial data stream to a 16 bit (or more generally an n-bit) parallel data value for sending to the TFT LCD module 150 as a parallel data stream 140. That is the image is never wholly contained in the multiplexor, rather it converts the data from 1-bit to n-bits as it is sent to the TFT LCD module. The multiplexer has input ports (or lines, the terms will be used interchangeably) A and B with input port A used to receive the first 16-bit parallel data value corresponding to the pixel off value 132 (eg white), and input port B used to receive the second 16-bit parallel data value corresponding to the pixel on value 133 (eg black). That is a 0 maps to white and a 1 maps to black. However as would be apparent to the person skilled in the art the TFT LCD is capable of colour (or at least multiple grey level) display and thus any two predefined (or preselected) colour values may be used. For example black on white, white on black, yellow on black, pink on blue, dark grey on light grey etc. At any one time only 2 colours are used on the display, with the choice of the two colours used selected by the user or installer via ports A and B. In an alternative embodiment the multiplexer is preconfigured with the first n-bit parallel data value and the second n-bit parallel data value. For example the values could be provided in a hardware form or stored in a memory. In another alternative embodiment the multiplexer may use a single input port (or line) to receive the first and second parallel data values which are then stored and used by the multiplexer.

[0022] The TFT LCD module 150 comprises a receiver 151 for receiving the parallel data stream 140 from the multiplexer 130, and a memory 152 which is used to store the received parallel data stream as 16-bit per pixel image (or n-bit per pixel) for display by the TFT LCD. That is each received pixel is stored as a 16 bit value 154. Depending upon the architecture of the memory, and the value of n, the received pixels may be stored in the memory in a compact packed form. The TFT LCD module may also comprise a LCD controller which is used to control the physical display of the image on the display and implements functions such as generation and sending of signals to turn pixels on or off, controlling the refresh rate, etc as would be apparent to the person skilled in the art. The receiver may be a component (or module) of a LCD controller or it may be operatively connected to such an LCD controller. The TFT LCD may be a single panel display or comprised of several display elements which are combined to form a composite panel.

[0023] In another embodiment the microprocessor 110 further comprises a Direct Memory Access (DMA) controller 1 13 (and any associated protocols) for transferring the 1 bit per pixel image from the microprocessor to the TFT LCD module via the multiplexer with minimal CPU overhead. DMA protocols and hardware effectively allow the reading/writing or transfer of memory between devices without supervision by the microprocessor. Thus if a DMA controller is present, or DMA protocols are supported, then little or no processor time is required to transfer the entire image once the transfer is started, and so the microprocessor 110 is freed up to perform other tasks. In this case (ie DMA used to feed the serial port) the CPU overhead is reduced significantly compared to a hardware SPI

implementation (as described above), as the CPU can set up a transfer of as many bytes as the DMA controller is capable of handling (eg 1024 in the embodiment described below). Many low cost microprocessors now support Direct Memory Address (DMA) transfers between memory and peripherals.

[0024] The method (or process) being implemented in the apparatus shown in Figure 1 is further illustrated in Figure 2 which is a flowchart 200 of a method for transferring a 1 bit per pixel image to an n bit per pixel image for display by a TFT LCD module. Step 210 comprises sending a 1 bit per pixel image from a microprocessor as a serial data stream to a multiplexer in which each pixel is represented as either a low data bit value or a high data bit value. At step 220 a multiplexer (or mux) maps the serial data steam to an n-bit parallel data stream (ie acts as a de-serialiser). Each serial data bit in the serial data stream is mapped to a n-bit parallel data value wherein each low data bit in the serial data stream is mapped to a first n-bit parallel data value, and each high data bit in the serial data stream is mapped to a second parallel n-bit data value. Then at step 230 sending the n-bit parallel data stream to a TFT LCD module comprising a TFT LCD and at step 240 the TFT LCD displays the received n-bit parallel data stream as n- bit per pixel (typically colour) image. As outlined above the TFT LCD module may comprise a LCD controller which includes a receiver for receiving the n-bit parallel data stream and which is used to control the physical display of the image (ie sending signals to turn pixels on or off, controlling the refresh rate, etc)

[0025] Turning to a specific implementation, FIGURE 3 is a circuit diagram 300 of an embodiment for displaying a 16-bit per pixel image on a TFT LCD. In this embodiment the microprocessor is a Texas Instruments LM3S5B91 microcontroller 310, the multiplexer is a Texas Instruments SN74LVC257A 320, and the TFT LCD module includes a Renesas Technology R61509V LCD controller 330 which receives the output from the multiplexer and which is used to drive a TFT LCD (not shown). In this embodiment the LCD controller uses a special 8 colour mode, in which only one bit of data is required for each of Red, Green, and Blue colour component. This allows use of a single 4-bit multiplexer chip. The controller must first be configured (by using the normal 16 bit parallel GPIO interface) to use this mode. The power supply and other components such as details of the TFT LCD, or other inputs related to the primary apparatus function have been omitted for clarity. It is to be understood that this represents one embodiment, and other functionally equivalent components or parts could be used in other embodiments as would be apparent to the person skilled in the art.

[0026] Once the LCD is initialised and ready to accept image data, the transfer can begin. Firstly the LCD_D0 - LCD_D15 lines, and LCD_WR line are set to high impedance output states. This allows the multiplexer to drive LCD_D4, LCD D10, LCD_D15, and LCD WR lines, by controlling the most significant bit (MSB) of each of the red green and blue (RGB) image components, and the write strobe. Lines LCD DO - LCD_D2 (connected to 1 A, 2A, and 3 A of the multiplexor), and LCD_D5 - LCD_D7 (connected to IB, 2B, and 3B of the multiplexor) are set to output, with the value on lines LCD DO - LCD_D2 defining the "Off colour for a pixel, and the value on lines LCD_D5 - LCD_D7 defining the "On" colour for a pixel. Line OE* is set to low to enable multiplexer output (ie setting of values). A DMA transfer of lbpp image data is started using the SSIO (serial) lines. The serial bit value is provided to the SEL input of the multiplexer to select between the "Off and "On" 16 bit colours defined by the values on lines LCD DO - LCD D2 and LCD_D5 - LCD_D7 respectively. The serial clock (SSIOCLK) drives the LCD write strobe (LCD_WR), latching a parallel word in the LCD controller for each data bit from the microcontroller.

[0027] An apparatus for converting a 1 bit per pixel image stored in a memory of a microprocessor to an n bit per pixel image using a serial peripheral interface and external multiplexer has been described along with an associated method. The multiplexer performs a hardware lookup to convert the 0 state to first n- bit predefined value and the 1 state to a second n-bit predefined value. This combination thus take a serial data stream and performs an on the fly conversion to a parallel data stream suitable to use by a TFT LCD for display as an n-bit per pixel image. This avoids the need for the memory to maintain a lookup table in software and for the processor to perform the conversion. Further the apparatus advantageously allows a low cost microprocessor to utilise the improved display capabilities of TFT displays and thus achieve a higher level of performance for the apparatus from a lower power system than would otherwise be possible.

[0028] This hardware based approach allows a low cost microprocessor (or microcontroller) to achieve the maximum possible image transfer speed supported by the display whilst running at a significantly lower processor speed than would otherwise be required. This in turn allows lower power consumption, and/or utilisation of a cheaper microprocessor to achieve a higher level of performance. It also requires much lower processor time utilization during the transfer than would otherwise be required, leaving the processor available for other tasks.

[0029] Colour TFT LCDs offer vastly superior contrast, response time and viewing angles compared to older STN LCDs. The use of a multiplexor as described above enables use of TFT displays in a wide range of LCD control panels and apparatus such as those found in lighting controllers, security system controllers, interfaces for building control systems, etc which typically use low cost microprocessor which are only effectively capable of storing images as 1 bit monochrome images and have insufficient resources to drive a TFT LCD (or other colour display). The multiplexor allows conversion of the 1 bit per pixel serial data stream into a n-bit (eg 2-, 4-, 8-, 16- etc bit) parallel data stream which can then be utilised by the TFT LCD. Further the low power consumption facilitates use in low cost portable devices such as air conditioner controllers, etc.

[0030] Those of skill in the art would understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0031] Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0032] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. For a hardware implementation, processing may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof. Software modules, also known as computer programs, computer codes, or instructions, may contain a number a number of source code or object code segments or instructions, and may reside in any computer readable medium such as a RAM memory, flash memory, ROM memory, EPROM memory, registers, hard disk, a removable disk, a CD- ROM, a DVD-ROM or any other form of computer readable medium. In the alternative, the computer readable medium may be integral to the processor. The processor and the computer readable medium may reside in an ASIC or related device. The software codes may be stored in a memory unit and executed by a processor. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

[0033] Throughout the specification and the claims that follow, unless the context requires otherwise, the words "comprise" and "include" and variations such as "comprising" and "including" will be understood to imply the inclusion of a stated integer or group of integers, but not the exclusion of any other integer or group of integers.

[0034] The reference to any prior art in this specification is not, and should not be taken as, an acknowledgement of any form of suggestion that such prior art forms part of the common general knowledge.

[0035] It will be appreciated by those skilled in the art that the invention is not restricted in its use to the particular application described. Neither is the present invention restricted in its preferred embodiment with regard to the particular elements and/or features described or depicted herein. It will be appreciated that the invention is not limited to the embodiment or embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention as set forth and defined by the following claims.