FOR CABLE LOSSES IN A C8PSK HART SYSTEM

BACKGROUND INFORMATION

[01] The present invention relates to the Highway Addressable Remote Transducer

("HART") system, and more specifically to equalizing cable losses in a C8PSK HART system.

[02] The HART protocol is a global standard for sending and receiving digital information across analog wires between intelligent field devices and a control system, and enhancing traditional 4-20mA signaling by simultaneously allowing two way digital communications. Fig. 1 illustrates a schematic diagram of a HART network. As shown, a HART network 100 includes a control room 101 and a number of field devices 110.1 - 110. n coupled to the control room 101. The field devices typically are instruments controlled by the control room 101, e.g., pressure sensors, control valves, etc. They collect information in response to a command from the control room 101 and communicate the information back to the control room 101 via the HART protocol. The control room 101 then controls the field device, e.g., 110.1, according to the information received from that field device. With the HART protocol, the control room 101 communicates with field devices to carry out device configuration or reconfiguration, device diagnostics and device troubleshooting without sending an engineer to the field. In Fig. 1, Rl - Rn and CI - Cn represent resistance and capacitance of communication lines interconnecting the field devices 110.1 - HO.n to the control room 101 respectively, and Rsense represents the load of the control room 101 to the network.

[03] Coherent 8-way Phase Shift Keying (C8PSK) is widely used in the telecommunication industry and is known for providing the best balance between faster communications and lower power consumption required for 2-wire field devices.

[04] Fig. 2 illustrates a schematic architecture of a transmitter in a prior art C8PSK HART field device. As shown, the input of a symbol mapping device 201 is coupled to the input of a transmitter 200. The symbol mapping device 201 receives incoming data stream at 9.6 Kbits per second, and divides the data stream into symbols, each of which is a group of three consecutive bits (tribit) and is mapped into a phase angle. The frequency of the output signal of the symbol mapping device 201 is 3.2 KHz.

[05] The input of a look up table (LUT) 202 is coupled to the output of the symbol mapping device 201 to receive the symbols. A symbol is used as a pointer of the LUT 202 to find out the symbol's real and imaginary parts. [06] A root raised cosine (RRC) filter 203 is coupled to the output of the LUT 202 to receive the imaginary part (Imag) of a symbol, and an RRC filter 204 is coupled to the output of the LUT 202 to receive the real part (Real) of the symbol. The RRC filters 203 and 204 filter the real and imaginary parts of the symbol and output a quadrature phase signal Q and an inphase signal I of the symbol respectively.

[07] One input of a mixer 205 is coupled to the output of the RRC 203 to receive the quadrature phase signal Q, and another input of the mixer 205 receives a carrier cos(rot). The mixer 205 multiplies Q and cos(rot).

[08] One input of a mixer 206 is coupled to the output of the RRC 204 to receive the inphase signal I, and another input of the mixer 206 receives a carrier sin(<at). The mixer 206 multiplies I and sin(<at).

[09] One input of an adder 207 is coupled to the output of the mixer 205 to receive the signal Q x cos(<at), and another input of the adder 207 is coupled to the output of the mixer 206 to receive the signal I x sin(<at). The adder 207 combines these two signals together and outputs Q x cos(<at)+ I x sin(<at), the signal to be transmitted.

[10] A digital to analog converter (DAC) 208 has an input coupled to the output of the adder 207, and converts the signal to be transmitted, Q x cos(<at)+ I x sin(<at), to an analog signal.

[11] An input of a buffer 209 is coupled to the output of the DAC 208. The analog signal is buffered at the buffer 209 before entering the transmit channel.

[12] The channel characteristics are different for each field device in a HART network, dependent on their distances from the control room. In prior art C8PSK HART systems, the control room does not have data representing the field devices' location and hence does not know the bandwidth of the cable between it and a field device. The cable bandwidth could cause large bit error rates at a control room receiver due to the no-linearity of the cable system.

[13] According to the C8PSK HART protocol, bandwidth limitations of a channel from a control room to a field device can be estimated and equalized by a channel estimation device in a receiver in the field device. However, neither the C8PSK HART standard nor prior art C8PSK HART field devices have transmitter side equalization.

[14] Therefore, it would be desirable to provide a method to adjust the signal from a field device to overcome cable bandwidth limitations and a field device which can compensate for the bandwidth limitations in its transmit channel, and to allow good reception in the control room irrespective of where the field device is in the network.

BRIEF DESCRIPTION OF THE DRAWINGS

[15] So that features of the present invention can be understood, a number of drawings are described below. It is to be noted, however, that the appended drawings illustrate only particular embodiments of the invention and are therefore not to be considered limiting of its scope, for the invention may encompass other equally effective embodiments.

[16] Fig. 1 illustrates a schematic diagram of a HART network.

[17] Fig. 2 illustrates a schematic architecture of a transmitter in a prior art C8PSK HART field device.

[18] Fig. 3 illustrates a schematic architecture of a transmitter in a C8PSK HART field device according to one embodiment of the present invention.

[19] Fig. 4 illustrates a schematic architecture of a C8PSK HART field device's receiver and transmitter according to one embodiment of the present invention.

[20] Fig. 5 illustrates simulated signals in a C8PSK HART system.

[21] Fig. 6 shows a method of equalizing a transmit channel in a C8PSK HART field device according to one embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[22] The present invention provides a method to adjust a waveform transmitted from a field device to a control room to overcome cable bandwidth limitations by passing the signal to be transmitted through a channel compensation device which pre-distorts the signal to be transmitted to compensate for the bandwidth limitations. The predistortion may improve signal quality when it is received at the control room.

[23] Fig. 3 illustrates a schematic architecture of a transmitter in a C8PSK HART field device according to one embodiment of the present invention. As shown, a channel compensation device 310 may be added to the transmitter in Fig. 2, with its input coupled to the output of the adder 207 and its output coupled to the input of the DAC 208. The signal to be transmitted may be pre-distorted by the channel compensation device 310 with the channel impairments to compensate for the bandwidth limitations. In one embodiment, the channel compensation device 310 may be an equalizer. For example, the equalizer may be a linear equalizer (e.g., an MMSE (minimum mean square error) equalizer and a zero forcing equalizer), a decision feedback equalizer, a blind equalizer, an adaptive Equalizer, a Viterbi equalizer, a BCJR equalizer, or a turbo equalizer. It should be understood that the channel compensation device 310 may be placed in other places in the transmitter, e.g., between the symbol mapping device 201 and the LUT 202.

[24] HART is a master/slave protocol, which means that a smart field device only "speaks" when "spoken to" by a master, which is the control room in the HART system. A HART transaction consists of a master command together with a slave response. The channel impairments obtained by the receiver in a field device may be used in channel compensation in the transmitter in the field device.

[25] Fig. 4 illustrates a schematic architecture of a C8PSK HART field device's receiver and transmitter according to one embodiment of the present invention. As shown, at a receiver 400 in a field device HO.n, a command from a control room 101 may be converted into a digital signal by an ana log -to-digital converter (ADC) 401 and then filtered by a channel selectivity filter 402. A channel estimation device 403 may estimate channel impairments and compensate for the channel impairments before demodulation at mixers 404 and 405. The channel impairments may then be used by the channel compensation device 310 in the transmitter 300 for predistortion before a signal to be transmitted enters the transmit channel.

[26] Specifically, an input of the ADC 401 may be coupled to the input of the receiver 400.

The ADC 401 may receive an analog signal from the HART network and convert it into a digital signal.

[27] An input of the channel selectivity filter 402 may be coupled to the output of the ADC

401. The channel selectivity filter 402 may filter the digital signal from the ADC 401 to pass only the wanted signal, i.e., C8PSK HART modulated signal. Out of band signals may be filtered.

[28] The channel estimation device 403 may have an input coupled to the output of the channel selectivity filter 402. The channel estimation device 403 may estimate channel impairments (field abnormalities), including both magnitude and phase impairments, and compensate for the channel impairments.

[29] Table 1 below shows the C8PSK message segments according to the C8PSK HART protocol. Table 1

[30] As shown, the preamble of a message has 40 symbols and is a fixed sequence known by the receiver 400. The channel estimation device 403 may compare the sequence it received with the preamble sequence in Table 1 to detect the channel impairments, and compensate for the channel impairments.

[31] In one embodiment, the channel estimation device 403 may be an equalizer. In one embodiment, the equalizer may be a linear equalizer (e.g., an MMSE equalizer and a zero forcing equalizer), a decision feedback equalizer, a blind equalizer, an adaptive Equalizer, a Viterbi equalizer, a BCJR equalizer, or a turbo equalizer.

[32] In one embodiment, the channel estimation device 403 may save the channel impairments in a memory which is accessible by the channel compensation device 310 in the transmitter in the same field device.

[33] In one embodiment, the channel estimation device 403 in the receiver may be applied to the transmitter 300 and used as the channel compensation device 310, so that the channel impairments estimated by the channel estimation device 403 in the receiver 400 of the field device may be used to pre-distort the signal to be transmitted by the transmitter 300 in the field device to the control room 101 to reduce or eliminate errors in the signal received by the control room 101.

[34] Fig. 5 illustrates simulated signals in a C8PSK HART system. A signal 501 is a signal received at a receiver 400 in a field device, which is distorted. A signal 502 is an ideal signal, having a symmetric trajectory and ending at +/-67.5 ⁰ . The channel estimation device 403 may receive the distorted signal 501 at its input, compensate for the channel impairments, and provide the ideal signal 502 at its output. Specifically, the channel estimation device 403 may rotate the distorted signal 501 to shift it down to become a signal 503, and adjust the magnitude of the signal 503 to make it narrower to become the ideal signal 502. In short, the channel estimation device 403 may create a thin rotated signal, that is both corrected for magnitude and phase distortion.

[35] Returning to Fig. 4, the compensated signal from the channel estimation device 403 may then pass through an IQ demodulator for the respective I and Q signals. The IQ demodulator may include mixers 404 and 405. One input of the mixer 404 may be coupled to the output of the channel estimation device 403 to receive the compensated signal, and another input of the mixer 404 may be coupled to a sine carrier. The mixer 404 may output the I signal. One input of the mixer 405 may be coupled to the output of the channel estimation device 403 to receive the compensated signal, and another input of the mixer 405 may receive the sine carrier with a 90° phase shift. The mixer 405 may output the y ^' Q signal.

[36] RRC finite impulse response (FIR) filters 406 and 407 may be coupled to the mixers

404 and 405 to receive the I and y ^' Q signals respectively and filter the signals.

[37] Inputs of a Tan ^_1 (Q/I) function 408 may be coupled to the outputs of filters 406 and

407 respectively to receive the filtered signals. The Tan ^_1 (Q/I) function may extract the symbol to find out its angle.

[38] Inputs of a symbol unmapping device 409 may be coupled to the output of the

Tan ^_1 (Q/I) function, and sign(I) and sign(Q). The symbol unmapping device 409 may divide a symbol into 3 bits to reproduce the transmitted bits.

[39] Clock data from a clock data recovery circuit 411 may be applied to the bits from the symbol unmapping device 409, and the bits may then enter a data buffer 410.

[40] The channel impairments detected by the channel estimation device 403 in the receiver 400 may be used to pre-distort the transmit signal. Returning to Fig. 3, the channel compensation device 310 in the transmitter 300 may learn the channel impairments from the channel estimation device 403 in the receiver 400, and then pre-compensate the magnitude and phase of the signal from the adder 207, so that when it is received at the control room it is correct. In one embodiment, the channel compensation device 310's input may be the ideal signal 502 shown in Fig. 5, and its output may be the distorted signal 501 in Fig. 5.

[41] Fig. 6 shows a method of equalizing a transmit channel in a C8PSK HART system according to one embodiment of the present invention. [42] At 601, the receiver 400 in the field device 110. n may receive an incoming signal, a command formatted according to Table 1, from the control room 101.

[43] At 602, the received signal may be converted into a digital signal by the ADC 401, and the digital signal may be filtered by the channel selectivity filter 402 to select the HART signal.

[44] At 603, the channel estimation device 403 may detect the channel impairments by comparing the preamble of the HART signal from the channel selectivity filter 402 and the preamble shown in Table 1, and equalize the magnitude and phase of the HART signal toward the message shown in Table 1.

[45] At 604, the equalized signal may go through mixers 404 and 405, RRC FIRs 406 and

407, the Tan ^_1 (Q/I) function 408, the symbol unmapping device 409 and the data buffer 410, as described above with reference to Fig. 4. The data, which is a command from the control room 101, may then be processed by the field device 110. n.

[46] The field device HO.n may send a data stream back to the control room 101 in response to the command. At 605, at the transmitter in the field device HO.n, the data stream may go though the symbol mapping device 201, the LUT 202, the RRCs 203 and 204, the mixers 205 and 206 and the adder 207, as described above with reference to Figs. 2 and 3.

[47] At 606, the channel compensation device 310 may pre-distort the signal from the adder 207, which is the signal to be transmitted, according to the channel impairments detected by the channel estimation device 403 in the receiver 400 of the field device.

[48] At 607, the compensated signal may be converted to an analog signal by the DAC

208. The analog signal may then be buffered by the buffer 209 and transmitted back to the control room 101.

[49] Further embodiments are also possible, which are the result of subsets of elements of, or variously combining elements of, embodiments described.