The invention has been developed in the context of a dimmer control circuit for an electric lamp and is hereinafter described in that context. However, it will be understood that the invention does have broader application, for example to a method of and apparatus for generating a voltage signal having a periodic waveform composed of merged signal portions within selected half-periods of a supply voltage.

BACKGROUND OF THE INVENTION A lamp dimmer control circuit normally incorporates a solid state ac switching device, such as a triac, and a gating circuit for gating the switching device into conduction for a selected conduction angle during each half-cycle of the supply voltage. The conduction angle is varied by adjusting the phase-angle at which the switching device is gated during each half-cycle and, hence, the lamp illumination level is controlled in accordance with the average level of current flow through the lamp during each half-cycle.

If the lamp circuit is substantially resistive, when the switching device is gated into conduction the voltage rise time across the lamp is substantially instantaneous, this resulting in the creation of high order Fourier (harmonic) components and, consequentially, resulting in the radiation of high frequency electromagnetic interference. The effect of this interference is limited, under constraints imposed by Regulatory Authorities, by incorporating an LC filter in circuit with the switching

device. However, with the ever increasing requirements for minimising radio frequency (rf) interference, the size of inductive/capacitive filter elements must be increased to a level where they cannot conveniently be housed within a wall switch unit and/or be increased to a level that makes them prohibitively expensive. This applies particularly to high power dimmer control devices, for example those that are rated at 500VA or higher.

The present invention seeks to minimise these problems by limiting the harmonic components of a controlled voltage waveform and, as a consequence, by reducing the need for rf filtering.

SUMMARY OF THE INVENTION Broadly defined, the present invention provides a method of generating an electrical signal and which comprises merging portions of first and second sinusoidal form signals in selected half-periods of the first signal to establish a hybrid waveform within the selected half-periods. The second signal portions are generated at a frequency which is significantly greater than that of the first signal.

The invention may also be defined in terms of an apparatus for use in generating an electrical signal having a hybrid waveform. The apparatus comprises a switching device which is arranged to be located in circuit with a load to which a first sinusoidal form voltage is applied in use of the apparatus, a gating circuit arranged to generate a biasing signal which changes (ie, rises or falls) sinusoidally at a rate which is significantly greater than the frequency of the first voltage and to apply the biasing signal to the switching device in selected half-periods of the first voltage whereby the waveform of the voltage across the load is formed as a merger of portions of the waveforms of the first voltage and a second sinusoidal form voltage that appears across the load with application of the biasing signal to the switching device.

In an alternative, preferred form the apparatus comprises a first switching device which is arranged to be

located in series with a load and in circuit with an alternating voltage supply for the load, a first gating circuit arranged to generate and apply gating signals to the first switching device at a selected phase angle in selected half-periods of the supply voltage, a second switching device located in parallel with the first switching device, and a second gating circuit arranged to generate and apply biasing signals to the second switching device in the selected half-periods of the supply voltage.

The second gating circuit is arranged to generate the biasing signals as portions of a sinusoidal form voltage signal which is generated at a frequency which is significantly greater than that of the supply voltage.

Also, means are provided for synchronising the first and second gating circuits to cause the second switching device to be biased into conduction immediately prior to gating of the first switching device, whereby the waveform of the voltage that appears across the load in use of the apparatus is formed as a merger of portions of the waveforms of the supply voltage and a second, sinusoidal form, voltage that appears across the load with application of the biasing signal to the second switching device.

It will be appreciated from the above definitions of the invention that the voltage that is applied to the load comprises a merger of two partial sinusoidal waveforms.

Thus, the resultant hybrid waveform will be composed of two fundamental frequencies and, assuming substantially uniform merging of the two partial waveforms, no significant harmonics of the fundamentals. This obviates or at least reduces the need for rf filtering.

In low power applications of the invention, such as in dimmer control circuits, most of the circuit elements may be embodied in an integrated circuit.

Depending upon the application of the invention, the periodic load voltage waveform may be non-alternating or, as would more normally be the case, alternating. In the latter case, the merging of the partial waveforms of the first and second voltages will be made during each

half-period of the first voltage.

The ratio of frequency (f2) of the second signal (or voltage) to the frequency (fl) of the first signal (or voltage) will be dependent upon the steepness required of the wavefront of the hybrid voltage waveform, and it is preferred that the ratio 2/fol will be equal to or greater than 4. For most practical applications, the ratio f/f will be within the range 500 to 5,000, and for a dimmer control circuit the ratio may be in the order of 2,000.

That is, for a supply voltage having a frequency of 50Hz, the second voltage will be generated with a frequency in the order of 100KHz.

The invention will be more fully understood from the following description of schematic and preferred embodiments of the invention. The description is provided with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a schematic representation of a circuit that embodies the principles of the invention, Figure 2 is a schematic representation of an alternative form of the circuit of Figure 1, Figure 3 shows graphically the voltages at the various points in the circuits as illustrated in Figures 1 and 2, Figure 4 shows diagrammatically a circuit in accordance with a preferred embodiment of the invention, Figure 5 shows graphically the voltages at various points in the circuit of Figure 4, Figure 6 shows a specific circuit arrangement that embodies the arrangement that is shown diagrammatically in Figure 4.

Figure 7 shows a schematic representation of a circuit which may be employed to implement the invention in an alternative manner from that shown in Figures 1 and 2, Figure 8 shows graphically the voltages at various points in the circuit of Figure 7, Figure 9 shows an alternative form of the circuit as illustrated in Figure 7, and

Figure 10 shows a graphical representation of the voltages at various points in the circuit of Figure 9.

DETAILED DESCRIPTION OF PREFERRED FORMS OF THE INVENTION As illustrated in Figure 1, the circuit includes a load in the form of an incandescent lamp 10 which is connected in series with a first solid state switching device in the form of a triac 11 and across a mains supply (ie, a source) voltage 12. A first gating circuit 13 is provided for applying a gating pulse to the triac at a selected phase-angle during each half-cycle (ie, during each half-period) of the supply voltage.

A second solid state switching device in the form of an FET 14 is connected in parallel with the triac 11 and across a rectifier bridge 15. Also, a second gating circuit 16 is provided for applying a gating (ie, a biasing) signal to the FET 14 immediately prior to gating of the triac during each half-cycle of the supply voltage.

For this purpose the outputs of the two gating circuits 13 and 16 are synchronised.

The first gating circuit 13 may be in the form of a conventional gating circuit of the type that customarily is employed for gating a triac in a lamp dimmer control circuit. The gating circuit 13 includes a potentiometer 13a for selectively varying the phase-angle at which the triac is gated into conduction during each half-cycle of the supply voltage.

The second gating circuit 16 includes an oscillator stage for generating a sinusoidal-form alternating voltage at a frequency f2 that is high relative to the frequency fl of the supply voltage 12. The oscillator voltage, labelled voltage V1 might typically have a frequency in the order of 100KHz.

Also, the second gating circuit 16 includes an output stage which is synchronised with the first gating circuit 13 to provide periodic biasing signals, each of which has a waveform corresponding to the peak-to-peak half-period of the oscillator stage output waveform and each of which has a voltage level V2 equal to the peak-to-peak voltage of the

oscillator stage output voltage V1. Each biasing signal from the second gating circuit 16 is generated during a time interval immediately preceding the generation of each gating pulse from the gating circuit 13.

Figure 2 of the drawings shows a schematic representation of an alternative form of the circuit which has been described above with reference to Figure 1 and like reference numerals are employed to identify like parts. However in the circuit of Figure 2, two FET's 14a and 14b are employed as an alternative to the single FET 14 shown in Figure 1, and two back-to-back diodes 17 are employed as an alternative to the bridge rectifier 15 as shown in Figure 1.

The operation of the circuits that are illustrated in Figures 1 and 2 may also be explained by reference to the voltage waveforms that are shown in Figure 3. The voltage waveform V1 is generated within the second gating circuit 16 and a biasing signal V2 having a voltage level equal to the peak-to-peak value of the voltage V1 is passed as an output signal once during each half-cycle of the supply voltage. The waveform of the supply voltage is shown by the dotted outline that is superimposed on the oscillator voltage V1, although the frequency scale of the voltage V2 is expanded greatly relative to that of the supply voltage for illustrative purposes. As indicated previously, the voltage V1 might typically be generated at a frequency of 100KHz, whilst the supply voltage frequency would normally alternate at a 50Hz or a 60Hz rate.

The successive signals V2 are applied as biasing signals to the gate of the FET 14 during successive half-cycles of the supply. Thus, the FET 14 is biased into conduction during each half-cycle of the supply, this resulting in the establishment of a voltage V4 across the load 10 during the period that the gating signal is applied to the FET. The voltage V4 across the load will have the same waveform and period as the biasing signal V2., and the amplitude of the voltage V4 will be determined by the gain of the FET to obtain merging of the waveforms of the

voltages of V1 and Vs as described below.

Immediately following generation of the voltage V4 across the load, the gating pulse V3 is generated by the gating circuit 13 and is applied to the gate of the triac 11. This results in the triac 11 being gated into conduction, and this in turn results in the establishment of a voltage Vs across the load during the remaining period of each half-cycle of the supply voltage following gating of the triac.

As a consequence, during each half-cycle of the supply voltage the two (partial) waveforms V4 and Vs merge into one another to create the hybrid voltage waveform Vu, S across the load, as shown in the lower graphical representation of Figure 3.

The circuit as shown in Figure 4 embodies all of the elements of that shown in Figure 1 and, here again, like reference numerals are employed to identify like components. The circuit includes a load in the form of a lamp 10 which is connected in series with a triac 11 across a main supply voltage 12, and a gating circuit 13 is provided for applying a gating signal to the triac at a selected phase-angle during each half-cycle of the supply voltage.

An FET 14 is connected in parallel with the triac 11 and across a rectifier bridge 15, and Figure 4 illustrates a preferred circuit arrangement for generating biasing signals to be applied to the FET 14.

The circuit arrangement, which may be considered in conjunction with the voltage waveforms shown in Figure 5, includes a bridge rectifier 20 which is connected across the supply 12 and which provides an input voltage V6 to a timer circuit 21. The timer circuit is employed to generate an output signal V, which is composed of a series of pulses that rise to a logical 1 level when the voltage V6 drops to 0 and which fall to a logical zero level following expiration of a selected time period t corresponding to a selected phase-angle during each half-cycle of the supply voltage. Thus, the period of each

pulse of the output signal V, may be adjustable between 0 and 10 milliseconds in the case of a 50Hz supply.

A signal generator 22 is provided for generating two synchronised output signals at a 100KHz rate. One of the output signals, a sinewave signal V8 is applied to an analogue switching circuit 23, and the other output signal comprises a square wave signal V9 which is applied to a flip-flop circuit 24.

The flip-flop circuit 24 functions to provide an output pulse V10 which corresponds to input signal Vg but only when the output signal V, from the timer circuit 21 goes low. Thus, the flip-flop circuit provides the output pulse Vlo at a selected interval during each half-cycle of the voltage V6.

The output voltage V. 10 from the flip-flop circuit 24 is employed to gate the analogue switching circuit 23, and the analogue switching circuit provides an output signal Vll.

Thus, the output signal Vll comprises a portion of the sinusoidal signal Vg that exists during the interval of the pulse Vlo which is provided as an output from the flip-flop circuit 24.

The output signal Vll is employed to bias the FET 14 into conduction once during each half-cycle of the supply 12. This results in the establishment of a voltage V13 across the load 10 which will have the same waveform as the pulse Vi. during the period of conduction of the FET.

The trailing edge of each output voltage pulse Vlo from the flip-flop circuit 24 is employed also to initiate an output pulse V12 from the triac gating circuit 13. The output pulse V12 is employed to gate the triac 11 once during each half-cycle of the supply immediately following gating of the FET 14. When the triac 11 is gated into conduction the voltage V13 across the load 10 will follow the waveform of the mains supply voltage 12 for the remaining period of the supply half-cycle during which triac gating is effected.

Thus, the total waveform of the load voltage V13 will comprise a merger of the two partial waveforms that flow

from successive biasing/gating of the FET 14 and the triac 11. As stated previously, each partial waveform has a (partial) sinusoidal form.

Figure 6 of the drawings shows a circuit arrangement that embodies the operating characteristics of the circuit that is illustrated diagrammatically in Figure 4. The circuit that is shown in Figure 6 has application to dimmer control of an incandescent lamp and the values of the electrical components as indicated in Figure 6 are applicable to a 1000VA circuit.

Figure 7 of the drawings illustrates an alternative approach to signal conditioning and shows a circuit which avoids the need for a triac and, hence, a triac gating circuit. In this alternative arrangement a signal generator 30 is provided for generating an output signal V 15 at a frequency of 100KHz. A following signal generator 31 is provided to generate a gating signal V16 having a leading edge that corresponds with one half-cycle of the output signal V15 and a trailing square wave portion during each half-cycle of the supply voltage 12.

The gating signal V16 is applied to the FET 14 and, when the FET is gated into conduction the voltage waveform V1, will appear across the load 10. Here again, as shown in Figure 8, the load voltage will be constituted by a merger of two sinusoidal voltage waveforms, one corresponding to a half-cycle of the voltage waveform V15 and the other being constituted by a portion of the supply voltage 12.

Figure 9 shows a circuit arrangement which is similar to that described above with reference to Figures 7 and 8, but one in which output signals V18 from the signal generator 31 have a trailing edge that is shaped as the waveform of the voltage output V 15 from the preceding generator 30. The signal waveforms are shown in Figure 10.

As further alternatives, the circuit of Figure 7 may be employed to produce the waveforms as shown in Figure 10, and the circuit of Figure 9 may be employed to produce the waveforms as shown in Figure 8.