received by the International Bureau on 02 October 2015 (02.10.2015)

1. A circuit comprising:

a first die comprising a first substrate and a plurality of active devices;

an integrated passive device comprising a first layer, a second substrate and a plurality of passive devices, wherein the second substrate comprises a plurality of vias, and wherein the plurality of passive devices are implemented at least on the first layer or the second substrate, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and

a second layer disposed between the first die and the integrated passive device, wherein the second layer comprises a plurality of pillars, wherein each of the plurality of pillars connects a corresponding one of the plurality of active devices to (i) one of the plurality of vias, or (ii) one of the plurality of passive devices,

wherein the first die, the integrated passive device and the second layer are disposed relative to each other to form a stack, and

wherein

the second layer comprises interconnect devices,

the interconnect devices connect the plurality of vias to a plurality of solder bumps,

the second layer is disposed on a first side of the integrated passive device,

the plurality of solder bumps are disposed on a second side of the integrated passive device opposite the first side, and

the first die is disposed on a side of the second layer opposite the integrated passive device.

2. The circuit of claim 1, further comprising:

a medium access control module configured to (i) receive data, and (ii) generate a signal comprising the data; and a physical layer module configured to transmit the signal, wherein the physical layer module comprises the plurality of active devices and the plurality of passive devices.

3. The circuit of claim 1, wherein the integrated passive device does not include an active device.

4. The circuit of claim 1, wherein the plurality of active devices comprises a plurality of transistors.

5. The circuit of claim 1, wherein:

the first die is a semiconductor die; and

the first die comprises a plurality of complementary metal-oxide semiconductor transistors.

6. The circuit of claim 1, wherein:

the first die is a silicon-on-insulator die; and

the first die comprises a plurality of metal-oxide-semiconductor field-effect transistors.

7. The circuit of claim 1, wherein:

the second substrate comprises glass; and

the plurality of vias comprise a through glass vias.

8. The circuit of claim 1, wherein:

the second substrate comprises silicon; and

the plurality of vias comprise through silicon vias.

9. The circuit of claim 1, wherein:

the integrated passive device includes a first metallization layer and a second metallization layer;

the first metallization layer comprises a plurality of first conductive elements; the second metallization layer comprises a plurality of second conductive elements;

the plurality of passive devices comprises an inductance;

the inductance is defined by the plurality of vias, the plurality of first conductive elements, and the plurality of second conductive elements; and

at least some of the plurality of pillars are connected to corresponding ones of the plurality of vias.

10. The circuit of claim 1, wherein:

the plurality of active devices include a first amplifier;

the first amplifier is configured to output an output signal;

the plurality of passive devices include an inductance; and

the inductance is configured to receive the output signal from the first amplifier and transmit the output signal to an antenna.

11. The circuit of claim 10, further comprising:

a second amplifier configured to output a second signal; and

a second inductance comprising an end,

wherein

the end of the second inductance is connected to an input of the first amplifier and to an output of the second amplifier, and

the first amplifier is configured to generate the output signal based on the second signal.

12. The circuit of claim 1, further comprising:

a third layer comprising a third substrate and a second plurality of passive devices, wherein the third layer does not comprise an active device;

the third layer is disposed on the integrated passive device;

the second layer is disposed on the third layer; and

the first die is disposed on the second layer.

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13. The circuit of claim 12, further comprising:

an intermediate layer disposed on the first die; and

a second die disposed on the intermediate layer, wherein the intermediate layer comprises a second plurality of pillars connecting the first die to the second die.

14. A method comprising:

forming a die to include a first substrate and a plurality of active devices;

forming an integrated passive device comprising a first layer, a second substrate and a plurality of passive devices, wherein the second substrate comprises a plurality of vias, wherein the plurality of passive devices are implemented on at least the first layer or the second substrate, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and

disposing a second layer between the die and the integrated passive device, wherein the second layer comprises a plurality of pillars, wherein the disposing of the second layer between the die and the integrated passive device includes

connecting each of the plurality of pillars to (i) a corresponding one of the plurality of active devices and to (ii) one of the plurality of vias or one of the plurality of passive devices, and

connecting at least some of the plurality of pillars to corresponding ones of the plurality of vias,

wherein the die, the integrated passive device and the second layer are disposed relative to each other to form a stack, and

wherein

the second layer comprises interconnect devices,

the interconnect devices connect the plurality of vias to a plurality of solder bumps,

the second layer is disposed on a first side of the integrated passive device,

the plurality of solder bumps are disposed on a second side of the integrated passive device opposite the first side, and

30 the die is disposed on a side of the second layer opposite the integrated passive device.

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