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Title:
METHOD AND APPARATUS FOR PARALLEL PROCESSING IN A GIGABIT LDPC DECODER
Document Type and Number:
WIPO Patent Application WO/2011/159089
Kind Code:
A2
Abstract:
A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-density parity check (LDPC) decoder associated with the receive path circuitry for decoding the encoded received signal. The LDPC decoder further comprises a memory for storing a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a -1 value; and a plurality of processing elements for performing LDPC layered decoding, wherein at least one processing element is operable to process in the same cycle a first row and a second row of the parity check H matrix.

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Inventors:
PISEK ERAN (US)
ABU-SURRA SHADI (US)
Application Number:
PCT/KR2011/004351
Publication Date:
December 22, 2011
Filing Date:
June 14, 2011
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD (KR)
International Classes:
H03M13/11; H04B1/06
Foreign References:
US20070043998A12007-02-22
US20070094568A12007-04-26
US20090013239A12009-01-08
US20090070659A12009-03-12
Attorney, Agent or Firm:
Y.P.LEE, MOCK & PARTNERS (1575-1 Seocho-dong Seocho-gu, Seoul 137-875, KR)
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Claims:



 
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