SIGNAL IN A TRANSMITTER CHAIN

TECHNICAL FIELD

The disclosure relates generally to a digital signal predistortion, and more particularly, to a method and an apparatus for predistortion of a digital signal in a transmitter chain.

BACKGROUND

An application of a digital pre-compensation in a transmitter has been known in optics for reducing a penalty introduced by non-linear components such as a power amplifier, PA, and an in-phase and quadrature modulator, IQM. The power amplifiers, PA, are essential components in overall performance and throughput of communication systems, but the power amplifiers are inherently nonlinear. The nonlinearity in the power amplifiers generates spectral re-growth, which leads to adjacent channel interference and violations of out-of-band emissions standards mandated by regulatory bodies. The nonlinearity in the power amplifiers also causes in-band distortion, which degrades a biterror-rate, BER, and data throughput of a communication system. The digital precompensation eliminates the non-linear effects and helps to relax specifications of main modules of the transmitter thus lowering its overall costs. A transmission of high-order modulation formats is enabled by the digital pre-compensation which thereby increases spectral efficiency of the communication system. The use of the digital pre-compensation further allows transmitting signals with different and higher symbol rates, which in turn allows employing different forward error correction, FEC, overheads so that the transmission can be adapted to parameters of a link.

The digital pre-compensation is applied in the transmitter and/or a receiver as part of a digital signal processing. In particular, the digital pre-compensation can be applied for mitigating a penalty caused by a limited electrical bandwidth of the transmitter and for reducing an impact of non-linear characteristics of IQM and/or PAs. There are different known methods of digital pre-compensation with different complexity and performance based on a feed-forward digital pre-emphasis, PE, and a digital predistortion, DPD. In the PE, a linear filter is applied, while the DPD nonlinearly pre-distorts an input signal. The DPD methods aim to copy a non-linear behaviour of the limiting components and inject the transmitted signal with an inverse of the non-linear function to linearize an output. The known DPD methods are mainly of two types. DPD methods of a first type, hereinafter - DPD-1, operate on 1 sample per symbol, SPS, signals. Computational complexity (hereinafter, a time complexity is referred to as the computational complexity or simply complexity, that is expressed as the number of required elementary operations on an input of size N, where elementary operations are assumed to take a constant amount of time on a given computer and change only by a constant factor when run on a different computer) of the DPD processing in this case is advantageously low, but DPD methods of this type has a limited performance as an upsampling is performed after the digital predistortion processing of an input signal and an 1 SPS feedback error signal is used for the pre-distortion algorithm adaptation.

DPD methods of a second type, hereinafter - DPD-2, operate on upsampled signals with a higher SPS, including the use of a high SPS feedback error signal, that provides for a higher performance of the communication system. The DPD methods of the second type are used when the high performance is of particular importance. However, the DPD processing in this case has a significantly higher complexity and thereby higher implementation costs.

In general, the performance of the known digital pre-compensation methods is limited by a level of complexity of the required processing. The known DPD methods do not allow achieving a higher performance of the system under the condition of low complexity of the digital signal processing.

Therefore, there arises a need to address the above-mentioned technical drawbacks in existing technologies to ensure an improved performance of a communication system with a digital predistortion while maintaining the complexity of the signal processing low.

SUMMARY

It is an object of the disclosure to provide a method and an apparatus for predistortion of a digital signal in a transmitter chain avoiding one or more disadvantages of the prior art. This object is achieved by features of the independent claims. Further implementation forms are apparent from the dependent claims, the description, and the figures.

The disclosure provides a method and an apparatus for predistortion of a digital signal in a transmitter chain.

According to a first aspect, there is provided a method of predistortion of a digital signal in a transmitter chain. The method comprises obtaining an input signal sampled at a first sampling rate. The method then comprises decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k_down and 1 are integers, 1 being from 1 to k_down. The method further comprises generating k_down model input signal subsets of equal length L, by applying a non-linear model to each of the k_down input signal subsets. The method also comprises generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down model input signal subsets. Each model input signal subset being multiplied by an adaptation coefficient, where k_up is an integer greater than k_down. The method then comprises generating a predistortion signal with a second sampling rate which is k_up/ k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

The predistortion method as described, on one hand, operates on a low SPS input signals, but on the other hand, it has a polyphase structure, where the input signal is decomposed into a plurality of subsets or phases of equal length which are processed separately, that provides for embedding the upsampling into the predistortion process itself. The method advantageously provides for upsampling of the digital signal with different upsampling factors, including float factors, as a part of the predistortion processing. The method thereby allows improving the overall system performance while maintaining the complexity of the digital signal processing low.

Optionally, the method comprises obtaining an error signal sampled at the second sampling rate decompressing the error signal into k up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up, and calculating k_up*k_down adaptation coefficients for the k_down model input signal subsets on the basis of the k_up error signal subset.

Each predistortion signal subset can be generated by summing up the k_down model input signal subsets, wherein each model input signal subset is multiplied by an adaptation coefficient.

Thereby, the predistortion method is fed back with a higher SPS error signal to improve the performance, but again, uses the polyphase structure, where the feedback error signal is decomposed into a plurality of subsets or phases of the same equal length to be processed separately, that provides for maintaining the complexity low.

The method can comprise determining, for each predistortion signal subset, the biggest adaptation coefficient among k_down adaptation coefficients of the k_down model input signal subsets to be combined for generating the given predistortion signal subset, and selecting a model input signal subset with the biggest adaptation coefficient as an only term that contributes to the given predistortion signal subset.

The first sampling rate can be 1 sample per second, SPS. In this case, the non-liner model can be a non-linear spline model. Furthermore, the applying of the non-linear spline model can comprise calculating spline functions using lookup tables.

According to a second aspect, there is provided an apparatus for predistortion of a digital signal in a transmitter chain. The apparatus comprises a feeder, a decomposer, an evaluator, a predistortion unit and a composer. The feeder is configured for obtaining an input signal sampled at a first sampling rate. The decomposer is configured for decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k_down and 1 are integers, 1 being from 1 to k_down. The evaluator is configured for generating k_down model input signal subsets of equal length L, by applying a non-linear model to each of the k_down input signal subsets. The predistortion unit is configured for generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down model input signal subsets, wherein each model input signal subset is multiplied by an adaptation coefficient. K_up is an integer greater than k_down. The composer is configured for generating a predistortion signal with a second sampling rate which is k_up/k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

The predistortion apparatus of the second aspect implements the predistortion method of the first aspect and provides for achieving all the effects and benefits thereof. The predistortion apparatus operates on a low SPS input signal and has the polyphase structure, where the input signal is decomposed into a plurality of subsets or phases of equal length which are processed separately, that provides for embedding the upsampling into the predistortion process itself. The apparatus advantageously provides for upsampling of the digital signal with different upsampling factors, including float factors, as a part of the predistortion processing. The apparatus thereby allows improving the overall system performance while maintaining the complexity of the digital signal processing low. The apparatus can be based on relatively low-cost hardware for generating nonlinear distortions.

Optionally, the apparatus comprises a feedback feeder and a feedback decomposer. The feedback feeder is configured for obtaining an error signal sampled at the second sampling rate. The feedback decomposer is configured for decompressing the error signal into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up. The predistortion unit can be further configured for calculating k_up*k_down adaptation coefficients for the k_down model input signal subsets on the basis of the k_up error signal subsets.

Optionally, the feedback feeder is configured for receiving an upsampled input signal having the second sampling rate from an upsampling unit, and a feedback signal sampled at the second sampling rate from a receiver chain, and summing up the upsampled input signal with the inverted feedback signal to obtain the error signal sampled at the second sampling rate.

The predistortion apparatus with the feedback decomposer as described enables the use of a higher SPS feedback error signal to improve the performance without a significant increase in the complexity. This is provided by the polyphase structure, where the feedback error signal is decomposed into a plurality of subsets or phases of the same equal length to be processed separately, that provides for maintaining the complexity low. The described configuration of the predistortion apparatus also allows conducting the upsampling and the digital pre-emphasis, PE, of the signal in parallel with the predistortion to further reduce the complexity of the digital signal processing in the transmitter.

Alternative to the above, the feedback feeder can be configured for receiving the input signal having the first sampling rate from the feeder and a feedback signal sampled at the first sampling rate from a receiver chain, summing up the input signal with the inverted feedback signal, each having the first sampling rate, to obtain the error signal having the first sampling rate, and upsampling the error signal to the second sampling rate to obtain the error signal sampled at the second sampling rate.

Optionally, the predistortion unit can be configured for generating each predistortion signal subset by summing up the k_down model input signal subsets, wherein each model input signal subset is multiplied by an adaptation coefficient. Alternative to the latter, the predistortion unit can be configured for determining, for each predistortion signal subset, the biggest adaptation coefficient among k_down adaptation coefficients of the k down model input signal subsets to be combined for generating the given predistortion signal subset, and selecting a model input signal subset with the biggest adaptation coefficient as an only term that contributes to the given predistortion signal subset. The rest of the k_down adaptation coefficients, except for the biggest one, can be discarded which allows reducing the complexity significantly with a minor impact in the performance.

The first sampling rate can be 1 sample per second, SPS. In this case, the evaluator can be configured for applying a non-linear spline model The evaluator can be further configured for calculating spline functions of the non-linear spline model using lookup tables. The use of the spline functions ant the lookup tables allows further improving the performance while decreasing the complexity.

According to a third aspect, there is provided a method of predistortion of a digital signal in a transmitter chain. The method comprises obtaining an input signal sampled at a first sampling rate. The method then comprises decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k_down and 1 are integers, 1 being from 1 to k_down. The method further comprises generating k_down groups of 3 model input signal subsets of equal length L, by applying a non-linear spline model to every input signal subset to generate a group of 3 model input signal subsets from every input signal subset. Each group comprises (i) a product of an input signal subset shifted by a first index and two spline functions of a real part of the input signal subset shifted by a second index and of an imaginary part of the input signal subset shifted by a third index, (ii) a product of the input signal subset shifted by the first index and two spline functions of two real parts of the input signal subset shifted by the second index and by the third index, and (iii) a product of the input signal subset shifted by the first index and two spline functions of two imaginary parts of the input signal subset shifted by the second index and by the third index. The method also comprises generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down groups of 3 model input signal subsets, wherein each model input signal subset is multiplied by an adaptation coefficient. The k_up is an integer greater than k down. The method also comprises generating a predistortion signal with a second sampling rate which is k_up/k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

The predistortion method of the third aspect provides for all the effects and advantages of the predistortion method of the first aspect and allows further decreasing the complexity due to the use of the spline model and possible use of lookup tables to calculate the spline functions as described below.

The method can further comprise obtaining an error signal sampled at the second sampling rate, decompressing the error signal into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up, and calculating k_up*k_down groups of 3 adaptation coefficients for the 3 model input signal subsets on the basis of the k_up error signal subset.

Optionally, each predistortion signal subset can be obtained by summing up the k_down groups of 3 model input signal subsets, each model input signal subset being multiplied by an adaptation coefficient.

Alternative to the above, the method can comprise determining, for each predistortion signal subset, a group of 3 adaptation coefficients having the biggest values among k_down groups of 3 adaptation coefficients of the k_down groups of 3 model input signal subsets to be combined for generating the given predistortion signal subset, and selecting a group of 3 model input signal subsets with the adaptation coefficients of the biggest values as an only term that contributes to the given predistortion signal subset.

The first sampling rate can be 1 sample per second, SPS. Also, the applying of the nonlinear spline model can comprise calculating the spline functions using lookup tables.

According to a fourth aspect, there is provided an apparatus for predistortion of a digital signal in a transmitter chain. The apparatus comprises a feeder, a decomposer, an evaluator, a predistortion unit and a composer. The feeder is configured for obtaining an input signal sampled at a first sampling rate. The decomposer is configured for decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down -th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k_down and 1 are integers, 1 being from 1 to k_down. The evaluator is configured for generating k_down groups of 3 model input signal subsets of equal length L, by applying a non-linear model to every input signal subset to generate a group of 3 model input signal subsets from every input signal subset. Each group comprises (i) a product of an input signal subset shifted by a first index and two spline functions of a real part of the input signal subset shifted by a second index and of an imaginary part of the input signal subset shifted by a third index, (ii) a product of the input signal subset shifted by the first index and two spline functions of two real parts of the input signal subset shifted by the second index and by the third index, and, (iii) a product of the input signal subset shifted by the first index and two spline functions of two imaginary parts of the input signal subset shifted by the second index and by the third index. The predistortion unit is configured for generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down groups of 3 model input signal subsets. Each model input signal subset is being multiplied by an adaptation coefficient, where k_up is an integer greater than k_down. The composer is configured for generating a predistortion signal with a second sampling rate which is k_up/k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

The predistortion apparatus of the fourth aspect implements the predistortion method of the third aspect and provides for achieving all the effects and benefits thereof. The apparatus in this case can also be based on relatively low-cost hardware for generating nonlinear distortions.

The apparatus can further comprise a feedback feeder and a feedback decomposer. The feedback feeder is configured for obtaining an error signal sampled at the second sampling rate. The feedback decomposer is configured for decompressing the error signal into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up. The predistortion unit can be further configured for calculating k_up*k_down groups of 3 adaptation coefficients for the k_down groups of 3 model input signal subsets on the basis of the k_up error signal subsets. The feedback feeder can be configured for receiving an upsampled input signal having the second sampling rate from an upsampling unit, and a feedback signal sampled at the second sampling rate from a receiver chain, and summing up the upsampled input signal with the inverted feedback signal to obtain the error signal sampled at the second sampling rate. Alternative to the latter, the feedback feeder can be configured for receiving the input signal having the first sampling rate from the feeder and a feedback signal sampled at the first sampling rate from a receiver chain, summing up the input signal with the inverted feedback signal, each having the first sampling rate, to obtain the error signal having the first sampling rate, and upsampling the error signal to the second sampling rate to obtain the error signal sampled at the second sampling rate.

Optionally, the predistortion unit can be configured for generating each predistortion signal subset by summing up the k_down groups of 3 model input signal subsets, each model input signal subset being multiplied by an adaptation coefficient.

Alternative to the latter, the predistortion unit can be configured for determining, for each predistortion signal subset, a group of 3 adaptation coefficients having the biggest values among k_down groups of 3 adaptation coefficients of the k_down groups of 3 model input signal subsets to be combined for generating the given predistortion signal subset, and selecting a group of 3 model input signal subsets with the adaptation coefficients of the biggest values as an only term that contributes to the given predistortion signal subset.

The first sampling rate can be 1 sample per second, SPS. At that, the evaluator can be configured for calculating spline functions of the non-linear spline model using lookup tables.

A technical problem of the prior art is solved with any of the methods and the apparatuses as described above, wherein the technical problem concerns limitations in existing communication systems, such as low performance and high complexity of the digital signal predistortion.

The present disclosure provides for embedding the upsampling into the predistortion process by means of the polyphase structure of the described predistortion methods and apparatuses which allows improving the performance of the digital signal processing while maintaining the complexity low. The methods and the apparatuses as disclosed can be implemented with different upsampling factors within the predistortion processing. Therefore, the use of the methods and the apparatuses as disclosed can reduce a penalty introduced to a communication system by non-liner characteristics of components, such as power amplifiers, PA, and in-phase and quadrature modulator, IQM, in an optimized and effective manner.

These and other aspects of the disclosure will be apparent from the implementations) described below.

BRIEF DESCRIPTION OF DRAWINGS

Implementations of the disclosure will now be described, by way of example only, with reference to the accompanying drawings in which:

FIG. 1A is a block diagram of an apparatus for predistortion of a digital signal in a transmitter chain in accordance with an implementation of the disclosure;

FIG. 1B is a block diagram of an apparatus for predistortion of a digital signal in a transmitter chain in accordance with another implementation of the disclosure;

FIGS. 2A-2B illustrate decomposing of an input signal into subsets or phases in accordance with implementations of the disclosure;

FIGS. 3A-3B illustrate decomposing of an error signal into subsets or phases in accordance with implementations of the disclosure;

FIGS. 4A-4B are diagrams that illustrate generating predistortion signal subsets in accordance with implementations of the disclosure;

FIG. 5 illustrates merging predistortion signal subsets into a predistortion signal in accordance with an implementation of the disclosure; FIGS. 6A-6B are block diagrams that illustrate a communication system with an apparatus for predistortion of the digital signal in a transmitter chain in accordance with implementations of the disclosure;

FIG. 7 is a flow diagram of a method of predistortion of a digital signal in a transmitter chain in accordance with an implementation of the disclosure;

FIG. 8 is a flow diagram of a method of predistortion of a digital signal in a transmitter chain in accordance with another implementation of the disclosure;

FIG. 9A is a graph illustrating a comparative data on the performance of the known digital predistortion methods (DPD-1 and DPD-2) and the Upsampling Digital Predistortion, UDPD, method in accordance with an implementation of the disclosure with a predistortion upsampling factor of 1.5;

FIG. 9B is a graph illustrating a comparative data on the performance of the known digital predistortion methods (DPD-1 and DPD-2) and the UDPD method in accordance with an implementation of the disclosure with a predistortion upsampling factor of 1.25;

FIG. 9C is a graph illustrating a comparative data on the performance of the known digital predistortion methods (DPD-1 and DPD-2) and the UDPD method in accordance with an implementation of the disclosure with a predistortion upsampling factor of 2.0.

DETAILED DESCRIPTION

Implementations of the disclosure provide methods and apparatuses for predistortion of a digital signal in a transmitter chain to improve the performance of the digital signal processing while maintaining the complexity low.

To make solutions of the disclosure more comprehensible for a person skilled in the art, the following implementations of the disclosure are described with reference to the accompanying drawings.

Terms such as "a first", "a second", "a third", and "a fourth" (if any) in the summary, claims, and the accompanying drawings of the disclosure are used to distinguish between similar objects and are not necessarily used to describe a specific sequence or order. It should be understood that the terms so used are interchangeable under appropriate circumstances, so that the implementations of the disclosure described herein are, for example, capable of being implemented in sequences other than the sequences illustrated or described herein. Furthermore, the terms "comprise" and "have" and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, a method, a system, a product, or a device that comprises a series of steps or units, is not necessarily limited to expressly listed steps or units, but it can comprise other steps or units that are not expressly listed or that are inherent to such process, method, product, or device.

Definitions:

DPD: Digital Pre-Distortion is one of the most cost-effective linearization techniques. It features an excellent linearization capability, the ability to preserve overall efficiency, and it takes full advantage of advances in digital signal processors and A/D converters. The technique adds an expanding nonlinearity in the baseband that complements the compressing characteristic of the radio frequency power amplifier. Ideally, the cascade of the pre-distorter and the power amplifier becomes linear and the original input is amplified by a constant gain. With a pre-distorter, the power amplifier can be utilized up to its saturation point while still maintaining good linearity, thereby significantly increasing its efficiency.

Upsampling: In digital signal processing upsampling is a term associated with the process of resampling in a multi-rate digital signal processing system. Upsampling can be synonymous with expansion, or it can describe an entire process of expansion and filtering (interpolation). When upsampling is performed on a sequence of samples of a signal or other continuous function, it produces an approximation of the sequence that would have been obtained by sampling the signal at a higher rate.

Downsampling: In digital signal processing, downsampling is a term associated with the process of resampling in a multi-rate digital signal processing system. Both downsampling and decimation can be synonymous with compression, or they can describe an entire process of bandwidth reduction (filtering) and sample-rate reduction. When the process is performed on a sequence of samples of a signal or other continuous function, it produces an approximation of the sequence that would have been obtained by sampling the signal at a lower rate.

FIG. 1A is a block diagram of an apparatus 100 for predistortion of a digital signal in a transmitter chain which can be referred to as an upsampling digital predistortion, UDPD, apparatus 100. The UDPD apparatus 100 comprises a feeder 102, a decomposer 104, an evaluator 106, a predistortion unit 108 and a composer 110. The feeder 102 is configured for obtaining an input signal sampled at a first sampling rate, having a length of N, i.e. including N samples. The decomposer 104 is configured for decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k down and 1 are integers, 1 being from 1 to k_down. The decomposing as described is illustrated in FIGS. 2A and 2B. K down can be referred to as a downsampling factor, wherein L is N/k_down. The evaluator 106 is configured for generating k_down model input signal subsets of equal length L, by applying a non-linear model to each of the k down input signal subsets. The predistortion unit 108 is configured for generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down model input signal subsets multiplied each by an adaptation coefficient. K_up is an integer greater than k down and can be referred to as an upsampling factor. The composer 110 is configured for generating a predistortion signal, which has a second sampling rate which is k_up/k_down times the first sampling rate, by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned. The generating of the predistortion signal from the predistortion signal subsets is illustrated in FIG.5. The ratio k = k_up/k_down can be referred to as a predistortion upsampling factor. The first sampling rate is a low SPS rate such as 1 SPS.

The UDPD apparatus 100 operates on a low SPS input signal and has the polyphase structure, where the input signal is decomposed into a plurality of subsets or phases of equal length which are processed separately, that provides for embedding the upsampling into the predistortion process itself. The UDPD apparatus 100 advantageously provides for upsampling of the digital signal with different upsampling factors k = k_up/k_down, including float factors, as a part of the predistortion processing. The UDPD apparatus 100 thereby allows improving the overall system performance while maintaining the complexity of the digital signal processing low. The UDPD apparatus 100 can be based on relatively low-cost hardware for generating nonlinear distortions.

The UDPD apparatus 100 further comprises a feedback feeder 112 and a feedback decomposer 114. The feedback feeder 112 is configured for obtaining an error signal sampled at the second sampling rate, having a length of k*N, i.e. including k*N samples, where k is the predistortion upsampling factor equal to k_up/k_down. The feedback decomposer 114 is configured for decompressing the error signal into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up. The decompressing of the error signal is illustrated in FIGS. 3A and 3B. The predistortion unit 108 is further configured for calculating k_up*k_down adaptation coefficients for the k_down model input signal subsets on the basis of the k_up error signal subsets.

The predistortion upsampling coefficient k equal to k_up/k_down is a floating-point number and can have different values depending on requirements and needs of the system performance. For example, the predistortion upsampling coefficient k can be 2.0 (i.e. 2/1), 1.5 (i.e. 3/2), 1.25 (i.e. 5/4) etc.

The feedback feeder 112 can be configured for receiving an upsampled input signal having the second sampling rate from an upsampling unit, and a feedback signal sampled at the second sampling rate from a receiver chain, and summing up the upsampled input signal with the inverted feedback signal to obtain the error signal sampled at the second sampling rate. An exemplary diagram of a communication system with the UDPD apparatus implementing such an upsampled feedback scheme is shown in FIG.6A. In this case the feedback feeder 112 and the feedback decomposer 114 operate with signals sampled at the second sampling rate, i.e. a high SPS sampling rate.

Alternatively, the feedback feeder 112 can receive the input signal having the first sampling rate from the feeder 102 and a feedback signal sampled at the first sampling rate from a receiver chain. In this case the feedback feeder 112 is configured for summing up the input signal with the inverted feedback signal, each having the first sampling rate, to obtain the error signal having the first sampling rate, and for upsampling the error signal to the second sampling rate to obtain the error signal sampled at the second sampling rate. An exemplary diagram of a communication system with the UDPD apparatus implementing such a non-upsampled feedback scheme is shown in FIG.6B.

The predistortion unit 108 can be configured for generating each predistortion signal subset by summing up the k_down model input signal subsets multiplied each by an adaptation coefficient. Thereby, k_down adaptation coefficients are used for generating each predistortion signal subset, and k_up*k_down adaptation coefficients are to be calculated for generating k_up predistortion signal subsets.

Optionally, the predistortion unit 108 can be configured for determining, for each predistortion signal subset, the biggest adaptation coefficient among k_down adaptation coefficients of the k_down model input signal subsets to be combined for generating the given predistortion signal subset. In this case the predistortion unit 108 is further configured for selecting a model input signal subset with the biggest adaptation coefficient as an only term that contributes to the given predistortion signal subset. The rest of the k_down adaptation coefficients, except for the biggest one, can be discarded which allows reducing the complexity significantly with a minor impact in the performance.

The evaluator 106 can be configured for applying a non-linear spline model. Furthermore, the evaluator 106 can be configured for calculating spline functions of the non-linear spline model using lookup tables. The use of the non-linear spline model enables the apparatus 100 to significantly reduce the complexity in the transmitter and improve the system performance.

FIG. IB is a block diagram of an apparatus 100A for predistortion of a digital signal in a transmitter chain which can be referred to as a UDPD apparatus 100A. The UDPD apparatus 100A comprises a feeder 102A, a decomposer 104A, an evaluator 106A, a predistortion unit 108A and a composer 110A. The feeder 102A is configured for obtaining an input signal of a length N sampled at a first sampling rate. The decomposer 104A is configured for decomposing the input signal into k_down input signal subsets of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k down and 1 are integers, 1 being from 1 to k down.

The evaluator 106A, in contrast to the evaluator 106 of FIG. 1A, is configured for generating k_down groups of 3 model input signal subsets (x_nl_reim, x_nl_rere and x_nljmim) of equal length L, by applying a non-linear model to eveiy input signal subset to generate a group of 3 model input signal subsets from every input signal subset. Each group comprises (i) a product of an input signal subset shifted by a first index and two spline functions of a real part of the input signal subset shifted by a second index and of an imaginary part of the input signal subset shifted by a third index (x_nl_reim), (ii) a product of the input signal subset shifted by the first index and two spline functions of two real parts of the input signal subset shifted by the second index and by the third index (x_nl_rere), and, (iii) a product of the input signal subset shifted by the first index and two spline functions of two imaginary parts of the input signal subset shifted by the second index and by the third index (x_nl_imim). The predistortion unit 108A is configured for generating k_up predistortion signal subsets of equal length L. Each predistortion signal subset is generated by combining the k_down groups of 3 model input signal subsets, wherein each model input signal subset is multiplied by an adaptation coefficient, as illustrated in FIG.4A. K_up is an integer greater than k_down. The composer 110A is configured for generating a predistortion signal with a second sampling rate which is k_up/k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned as illustrated in FIG. 5. The first sampling rate can be 1 SPS.

The UDPD apparatus 100A provides for all the effects and benefits of the UDPD apparatus 100 described above with reference to FIG. 1 A and it additionally features the use of spline functions as the non-linear model for generating the input signal subsets which allows further reducing the complexity of the transmitter and improving the performance. At that, the UDPD apparatus 100A can be based on relatively low-cost hardware for generating nonlinear distortions. The apparatus 100A further comprises a feedback feeder 112A and a feedback decomposer 114A. The feedback feeder 112A is configured for obtaining an error signal of a length k*N sampled at the second sampling rate. The feedback decomposer 114A is configured for decompressing the error signal into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up, as illustrated in FIG. 3 A. The predistortion unit 108A is further configured for calculating k_up*k_down groups of 3 adaptation coefficients for the k_down model input signal subsets on the basis of the k_up error signal subsets.

The feedback feeder 112A can be configured for receiving an upsampled input signal having the second sampling rate from an upsampling unit, and a feedback signal sampled at the second sampling rate from a receiver chain, and for summing up the upsampled input signal with the inverted feedback signal to obtain the error signal sampled at the second sampling rate. An exemplary diagram of a communication system with the UDPD apparatus implementing such an upsampled feedback scheme is shown in FIG.6A.

Alternatively, the feedback feeder 112A can be configured for receiving the input signal having the first sampling rate from the feeder 102A and a feedback signal sampled at the first sampling rate from a receiver chain, summing up the input signal with the inverted feedback signal, each having the first sampling rate, to obtain the error signal having the first sampling rate, and for upsampling the error signal to the second sampling rate to obtain the error signal sampled at the second sampling rate. An exemplary diagram of a communication system with the UDPD apparatus implementing such a non-upsampled feedback scheme is shown in FIG.6B.

The predistortion unit 108A can be configured for generating each predistortion signal subset by summing up the k down groups of 3 model input signal subsets (x_nl_reim, x_nl_rere and x_nl_imim) multiplied each by an adaptation coefficient (W_reim, W_rere,W_imim), as illustrated in FIG. 4A.

Optionally, the predistortion unit 108A can be configured for determining, for each predistortion signal subset, a group of 3 adaptation coefficients (W_reim, W_rere, W_imim) having the biggest values among k down groups of 3 adaptation coefficients of the k_down groups of 3 model input signal subsets to be combined for generating the given predistortion signal subset. In this case the predistortion unit 108A is configured for selecting a group of 3 model input signal subsets with the adaptation coefficients of the biggest values as an only term that contributes to the given predistortion signal subset, as illustrated in FIG. 4B. The evaluator 106A is configured for calculating spline functions of the non-linear spline model using lookup tables.

FIGS. 2A and 2B illustrate decomposing an input signal into subsets or phases in accordance with implementations of the disclosure, for example, by the decomposer 104, 104A. FIG. 2A relates to a generic case where the input signal 202 of a length N is decomposed into k_down subsets 204A, 204B, 204C of equal length L. FIG. 2B relates to a special case where k_down equals 2, and the input signal 202A is decompressed into 2 subsets 204D and 204E. As shown, the input signal is decomposed into k_down input signal subsets by sequentially assigning each k_down-th sample of the input signal starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number, where L, k_down, and 1 are integers, 1 being from 1 to k down.

FIGS. 3A and 3B illustrate decomposing an error signal into subsets or phases in accordance with implementations of the disclosure, for example, by the feedback decomposer 114, 114A. An error signal 302 of a length k*N is sampled at a second sampling rate, wherein k is the predistortion upsampling factor defined as a ratio k_up/k_down. FIG. 3 A relates to a generic case where the error signal 302 is decomposed into k_up subsets (304A, 304B) of equal length L. As shown, the error signal 302 includes k*N samples that are divided into k_up error signal subsets of equal length L by sequential assigning each k_up-th sample of the error signal 302, starting with an p-th sample, to an p-th error signal subset (304A, 304B) in ascending order of sample number, p being from 1 to k_up. FIG. 2B relates to a special case where k_up equals 3, and the input signal 302A is decompressed into 3 subsets 304C, 304D and 304E.

In accordance with the disclosure, k_down input signal subsets of equal length L, obtained in result of the decomposing of the input signal as described above with reference to FIGS.2A and 2B, are subject to applying a non-liner model for generating model input signal subsets of equal length L, for example, by the evaluator 106 or 106 A. The evaluator 106 is configured for generating k_down model input signal subsets of equal length L, by applying a non-linear model to each of the k_down input signal subsets. The evaluator 106A is configured for generating k down groups of 3 model input signal subsets of equal length L, by applying a non-linear model to every input signal subset to generate a group of 3 model input signal subsets from each input signal subset.

In the content of the preset disclosure, the non-linear model can be any memory model. However, a better performance of the system in terms of complexity can be achieved by using a non-linear spline model. Splines are polynomial curves for interpolation or approximation of a sequence of Q+l points or knots Qi. Each knot Qi can be presented by a real part of the input signal and an imaginary part of the input signal:

The sequence of the knots is defined so as q _x,0 < q _x,1 < ... < q _x,Q, where q _x,0 is a minimum value of the input signal, q _x,Q is a maximum value of the input signal. That is, a range of the input signal is divided into Q subintervals.

Spline function of degree 1 is defined as follows:

Each input signal subset can be presented by a group of 3 model subsets as shown in FIG. IB:

where is an l-th input signal subset shifted by a first index j ₁ , I being from 1 to k_down, is the spline function as defined above of a real part of the l-th input signal subset shifted by a second index j ₃ , is the spline function of an imaginary part of the input signal subset shifted by a third index j ₂ , j _1, j ₂ ,j ₃ shift indexes, and i ₁ i ₂ are knot indexes of the spline function.

In case the input signal is sampled at 1 SPS sampling rate, each sample of the input signal can be interpolated by a spline function with a single knot, equals to 1, which means that the model input signal subsets can be generated using lookup tables, LUT, for calculating the spline functions. This can significantly reduce the complexity of calculations and improve the performance. In this case, each input signal subset can be presented by a group of 3 model input signal subsets: , where LUT _reim (j ₂ ,j ₃ ,i ₁ ,i ₂ ) =

LUT _re (j ₂ ,j ₃ ,i ₁ ,i ₂ ) = , and

LUT _im (j ₂ ,j ₃ ,i ₁ ,i ₂ ) = I being from 1 to k_down. The above formulas represent k_down groups of 3 model input signal subsets of equal length L that are generated by the evaluator 106A and provided to the predistortion unit 108A as illustrated in FIG. IB. The predistortion unit 108A is configured for generating k_up predistortion signal subsets of equal length L based on the k_down groups of 3 model input signal subsets. Each predistortion signal subset is generated by combining the k_down groups of 3 model input signal subsets multiplied each by an adaptation coefficient. Thus, 3*k_down adaptation coefficients are to be used for generating each predistortion signal subsets, and k_up*3*k_down adaptation coefficients are to be used for generating all the k_up predistortion signal subsets.

The predistortion unit 108A can be also provided with k_up error signal subsets of equal length L from the feedback decomposer 114A. The error signal subsets can be used for updating the predistortion algorithm by updating the adaptation coefficients applied by the predistortion unit 108A to the model input signal subsets. For this end, the predistortion unit 108A is configured for calculating k_up*k_down groups of 3 adaptation coefficients for the k_down groups of 3 model input signal subsets on the basis of the k_up error signal subsets.

In an embodiment, the predistortion algorithm update comprises calculating the adaptation coefficients for each model input signal subset by a least squares (LS) method. The method of least squares is based on a criterion according to which an estimation of parameters is optimal if a sum of error squares is minimal. Thus, the LS criterion is defined as follows: where err(n) = d(n) — y(n), an error between a desired signal d(n) and an output signal y(n).

Adaptation coefficients can be obtained by solving in the LS sense an overdetermined linear system V _l · W _lp = err _p . The LS estimate is given by where (V ₁ *V ₁ ) ^-1 V ₁ * is known as a pseudo-inverse of V _l , V _l is an l-th model input signal subset, / being from 1 to k down, p being from 1 to k_up, are former adaptation coefficients applied for generating the predistortion signal subsets on previous iteration (i.e. the coefficients used before the current predistortion algorithm update), μ is a weight of new coefficients, μ = (0,1], λ is a “memory” of former coefficients, λ = (0,1], reg = is a regularization function matrix, where E is unit matrix, and a is a regularization parameter.

In case of generating the k_down groups of 3 model input signal subsets as defined above, the adaptation coefficients can be calculated as follows:

Depending on the nonlinearity of the system, that is, on a gain and on a variance of the error, it is necessary to change the regularization parameter as follows: where var(err) is the variance of the error, G is the gain parameter of a power amplifier in decibels, dB.

FIG. 4A illustrates the generating of the k_up predistortion signal subsets x_udpd _p , p being from 1 to k_up, in accordance with an implementation of the disclosure, using the adaptation coefficients W _lPreim , W _lPrere , W _lPimim that can be calculated by the above formulas. In FIG. 4 A, there is a summing of k_down terms for generating each predistortion signal subset, wherein each one of the k_down terms is a corresponding model input signal subset multiplied by a corresponding adaptation coefficient:

FIG. 4B illustrates an optional optimization of the predistortion algorithm for reducing the computational complexity. The fact is that some terms to be summed for generating each predistortion signal subset can have small adaptation coefficients. For the optimization, the biggest adaptation coefficient, or a group of 3 adaptation coefficients having the biggest values, can be determined for each predistortion signal subset. Then, a model input signal subset with the biggest adaptation coefficient, or a group of 3 model input signal subsets with the adaptation coefficients of the biggest values, can be selected as an only term that contributes to the given predistortion signal subset. All the rest terms can be discarded. Experience has shown that the optimization as described allows significantly reducing the complexity of the predistortion processing at the expense of minor impact in the overall performance of the communication system.

FIG. 5 illustrates merging the predistortion signal subsets 502, 504 and 506 into a predistortion signal 508 in accordance with an implementation of the disclosure. The predistortion signal 508 has a second sampling rate which is k_up/k_down times a first sampling rate, k_up is an integer greater than k_down. As shown in FIG.5, the merging of the k_up predistortion signal subsets 502, 504, 506 comprises sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

FIGS. 6A and 6B are block diagrams of exemplary communication systems with an apparatus for predistortion of a digital signal, which can be referred to a UDPD apparatus, in a transmitter chain in accordance with implementations of the disclosure that differ from each other by a feedback scheme. Each of the communication systems in FIGS. 6A and 6B comprises a transmitter 602 and a receiver 604 in communication with each other through an optical channel 612. The transmitter 602 comprises the apparatus for predistortion of a digital signal or the UDPD apparatus 606, an upsampling module 608, and a digital pre-emphasis module 610. The receiver 604 comprises a root raised cosine, RCC, filter module 614, an adaptive finite impulse response, FIR, filter module 616, and a downsampling module 618. The UDPD apparatus 606 is provided with an input signal sampled at a first, low SPS, sampling rate and an error signal sampled at a second, high SPS, sampling rate to generate a predistortion signal having the second, high SPS, sampling rate. In FIG. 6A the error signal sampled at the second, high SPS, sampling rate is provided to the UDPD apparatus from the receiver chain. FIG. 6B illustrates another implementation of the communication system where the error signal from the receiver chain is sampled at the first, low SPS, sampling rate. In this case, the error signal is subject to upsampling, by an upsampling module 620, to the second, high SPS, sampling rate before feeding to the UDPD apparatus 606.

As described above, the UDPD apparatus 606 has a polyphase structure, where the input and error signals are decomposed into a plurality of subsets or phases which are processed separately, that provides for an improved performance of the system while maintaining the complexity low. The UDPD apparatus 606 allows conducting the upsampling and the pre-emphasis processing in parallel with the predistortion processing which allows reducing the complexity of these processes as well as the overall complexity of the digital processing in the system.

FIG. 7 is a flow diagram of a method of predistortion of a digital signal in a transmitter chain, which can be referred to as a UDPD method, in accordance with an implementation of the disclosure. At a step 702 of the UDPD method, an input signal sampled at a first sampling rate is obtained. At a step 704, the input signal is decomposed into k_down input signal subsets or phases of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number where L, k down and 1 are integers, 1 being from 1 to k_down. At a step 706, k_down model input signal subsets of equal length L are generated, by applying a non-linear model to each of the k_down input signal subsets. At a step 708, k_up predistortion signal subsets of equal length L are generated. Each predistortion signal subset is generated by combining the k_down model input signal subsets multiplied each by an adaptation coefficient, where k_up is an integer greater than k_down. At a step 710, a predistortion signal is generated with a second sampling rate which is k_up/k_down times the first sampling rate by sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

The UDPD method as described above has the polyphase structure that provides for embedding an upsampling into the predistortion process and thereby allows increasing the performance of the digital signal processing while maintaining the complexity low. The method can be implemented with different upsampling factors within the predistortion processing. Therefore, the use of the method as described allows reducing a penalty introduced to a communication system by non-liner characteristics of components such as power amplifiers, PA, and in-phase and quadrature modulator, IQM, in an optimized and effective manner.

The UDPD method can further comprise (i) obtaining an error signal sampled at the second sampling rate, (ii) decompressing the error signal into k_up error signal subsets or phases of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up, and (iii) calculating k_up*k_down adaptation coefficients for the k_down model input signal subsets on the basis of the k_up error signal subset. At that, each predistortion signal subset can be generated by summing up the k_down model input signal subsets multiplied each by an adaptation coefficient.

Optionally, the UDPD method can comprises determining, for each predistortion signal subset, the biggest adaptation coefficient among k_down adaptation coefficients of the k_down model input signal subsets to be combined for generating the given predistortion signal subset, and selecting a model input signal subset with the biggest adaptation coefficient as an only term that contributes to the given predistortion signal subset.

The first, low sampling rate can be of 1 SPS. The non-liner model can be a non-linear spline model, and the applying of the non-linear spline model can comprise calculating spline functions using lookup tables.

FIG. 8 is flow diagram of a method of predistortion of a digital signal in a transmitter chain, which can be referred to as a UDPD method, in accordance with another implementation of the disclosure, where a group of 3 model input signal subsets is generated from every input signal subset by applying to it a non-linear spline model. Namely, at a step 802, an input signal sampled at a first sampling rate is obtained. At a step 804, the input signal is decomposed into k_down input signal subsets or phases of equal length L by sequentially assigning each k_down-th sample of the input signal, starting with an 1-th sample, to an 1-th input signal subset in ascending order of sample number where L, k down and 1 are integers, 1 being from 1 to k_down. At a step 806, k_down groups of 3 model input signal subsets of equal length L are generated by applying a non-linear spline model to every input signal subset to generate a group of 3 model input signal subsets from every input signal subset. Each group comprises (i) a product of an input signal subset shifted by a first index and two spline functions of a real part of the input signal subset shifted by a second index and of an imaginary part of the input signal subset shifted by a third index, (ii) a product of the input signal subset shifted by the first index and two spline functions of two real parts of the input signal subset shifted by the second index and by the third index, and (iii) a product of the input signal subset shifted by the first index and two spline functions of two imaginary parts of the input signal subset shifted by the second index and by the third index. At a step 808, k_up predistortion signal subsets of equal length L are generated. Each predistortion signal subset is generated by combining the k down groups of 3 model input signal subsets, where each model input signal subset is multiplied by an adaptation coefficient, and k_up is an integer greater than k_down. At a step 810, a predistortion signal is generated with a second sampling rate which is k_up/k_down times the first sampling rate, by merging the k_up predistortion signal subsets. The merging of the k_up predistortion signal subsets comprises sequentially assigning one sample from each predistortion signal subset, in ascending order of subset number, from 1 to k_up, to the predistortion signal until all samples of the k_up predistortion signal subsets are assigned.

This implementation of the UDPD method provides for all the effects and advantages of the UDPD method described with reference to FIG. 7 and allows further decreasing the complexity due to the use of the spline model and possible use of lookup tables to calculate the spline functions.

The UDPD method can further comprise (i) obtaining an error signal sampled at the second sampling rate, (ii) decompressing the error signal into k_up error signal subsets or phases of equal length L by sequential assigning each k_up-th sample of the error signal, starting with an p-th sample, to an p-th error signal subset in ascending order of sample number, p being from 1 to k_up, and (iii) calculating k_up*k_down groups of 3 adaptation coefficients for the 3 model input signal subsets on the basis of the k_up error signal subset.

At that, each predistortion signal subset can be generated by summing up the k_down groups of 3 model input signal subsets, where each model input signal subset is multiplied by an adaptation coefficient.

Optionally, the UDPD method can comprises (i) determining, for each predistortion signal subset, a group of 3 adaptation coefficients having the biggest values among k_down groups of 3 adaptation coefficients of the k_down groups of 3 model input signal subsets to be combined for generating the given predistortion signal subset, and, (ii) selecting a group of 3 model input signal subsets with the adaptation coefficients of the biggest values as an only term that contributes to the given predistortion signal subset. The first sampling rate can be 1 SPS, and the applying of the non-linear spline model can comprises calculating the spline functions using lookup tables.

The complexity of the UDPD processing in the methods and apparatuses of the present disclosure can be calculated, for example, by cost table of 7 nm process metal-oxide- semiconductor field-effect transistors, MOSFETs, of Taiwan Semiconductor Manufacturing Company, TSMC, depending on the number of required multiplications and additions for different bit depths of the input signal and the adaptation coefficients.

In case of using the non-linear spline model and calculating the spline functions with the lookup tables as described above, the whole UDPD processing to obtain an p-th output predistortion signal subset or phase can be defined as follows:

It can be seen that the UDPD processing as written above comprises 2 additions of the adaptation coefficients additions of the adaptation coefficients due to a memory parameter of M, M multiplications of the input signal samples and the adaptation coefficients [x _inl (n — j ₃ ) • W], M-1 additions of results of said multiplications and k _down — 1 additions of the terms. In case the input signal is a 16-quadrature amplitude modulation, QAM, signal with 1 SPS sampling rate, the bit depth of the input signal samples can be set to 2 bits. The predistortion signal is an upsampled signal having k SPS sampling rate in accordance with the disclosure, thereby it requires a minimum of 6 bits, depending on the adaptation coefficients bit depth. The adaptation coefficients bit depth can be set in a range of 4 bits to 10 bits, depending on a required performance of the system.

For example, for input signal, 8 bits of the adaptation coefficients, 8 bits of the output predistortion signal, and M = 2 of the memory parameter, the overall complexity of the UDPD processing to obtain an output predistortion signal subset of length L = N/k_down can be calculated as follows:

Thereby, the complexity of the UDPD processing to obtain all the k_up predistortion signal subsets is:

C _UDPD = C _UDPD1 · k_up = 10621 · N gates.

The overall complexity of the optimized UDPD processing can be calculated as follows:

The computational complexity of the proposed UDPD method and apparatus as calculated above can be compared with the complexity of the known DPD methods of two types mentioned in the Background section.

The complexity of the known DPD method of the first type (hereinafter - DPD-1) that operates on 1 SPS input and error signals of length N and uses the same functions and parameters as set above for the UDPD method complexity estimate can be calculated as ws:

C _DPD1 = ((M - 1) · 41 + M · [80 + (M · M - 1) · 41 + M • M · 82]) · N

= 3520 • N gates

The complexity of the known DPD method of the second type (hereinafter - DPD-2) that operates on upsampled to k SPS input and error signals of length N and uses the same functions and parameters as set above for the UDPD method complexity estimate can be calculated as follows:

C _DPD2 = (((166 + 41) * 2) + 634 * 3) * M * M * 2 * 2 + M * 317 * 2 + (M * M - 1)

* (2 * 2 - 1) * 41 + M * 41 + (M - 1) * 41) · N • k

= 129700 · N gates

Thereby, the complexity of the UDPD methods of the present disclosure, especially the optimized one, is much closer to the low complexity of the known DPD method of the first type (DPD-1) that operates on 1 SPS signals, than to the high complexity of the known DPD method of the second type (DPD-2) that operates on upsampled k SPS signals.

Finally, the performance of the UDPD methods of the present disclosure can be compared with the performance of the known DPD methods.

FIGS. 9A to 9C illustrate a comparative data on the performance of the known digital predistortion methods, DPD-1 and DPD-2, and the optimized UDPD method of the disclosure with different predistortion upsampling factors (simply the upsampling factors in the known methods) k = 1.5 (FIG. 7 A), 1.25 (FIG. 7B) and 2.0 (FIG. 7C).

For the comparative analysis, the known DPD-1 and DPD-2 methods have been implemented as follows. In an implementation of the DPD-1 method, an input signal sampled at 1 SPS rate is subject to, in a transmitter chain, the predistortion processing, the upsampling to k SPS sampling rate, and the feed-forward digital PE, all that in sequence. The k SPS signal is transmitted via an optical channel and, in a receiver chain, is subject to the RRC filtering, the FIR filtering and the downsampling to 1 SPS sampling rate. Said downsampled, 1 SPS signal is fed back to the transmitter chain as a feedback error signal for adaptation of the predistortion algorithm.

An implementation of the DPD-2 method differs from the DPD-1 one described above in that the 1 SPS input signal is at first upsampled to k SPS sampling rate and then subject to the predistortion and the PE processing which are made in parallel. In the received chain, the signal is fed back to the transmitter chain before the downsampling to provide a k SPS feedback error signal for adaptation of the predistortion algorithm.

A communication system with the UDPD apparatus for predistortion of the digital signal in a transmitter chain that can be used for an implementation of the optimized UPDP method is shown in FIG. 6A, with the UDPD apparatus structure illustrated in FIG. IB. Correspondingly, in an implementation of the optimized UDPD method, the 1 SPS input signal is decompressed into k_down subsets or phases, as shown in FIG. 2A, while the k SPS feedback error signal is decompressed into k_up subsets or phases, as shown in FIG. 3A. For this comparative analysis, the optimized UDPD processing has been implemented by means of the non-linear spline model with calculating the spline functions using the lookup tables as described above and illustrated in FIG. 4B.

FIGS. 7a to 7C show the performance of each of the predistortion methods in the analysis, which is defined by a normalized mean square error, NMSE, in dB, between a desired signal and an output signal, depending on iterations of the predistortion algorithm. It can be seen that in each case the performance of the optimized UDPD method is in between the performances of the known methods, surpassing the DPD-1 method which also operates on 1 SPS signals.

Although the disclosure, its effects and advantages have been described in detail with reference to certain implementations, it should be understood that all the details are provided for illustrative purposes only and various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.