Title:
METHOD AND APPARATUS FOR PROCESSING COMPOUND SEMICONDUCTOR WAFER
Document Type and Number:
WIPO Patent Application WO/2011/083667
Kind Code:
A1
Abstract:
Disclosed is a polishing method whereby chipping and breaking failures of a compound semiconductor wafer can be reduced. The method for polishing the compound semiconductor wafer, i.e., a method for lapping both the surfaces of the compound semiconductor wafer, includes a step of lapping the semiconductor wafer by disposing the semiconductor wafer between the upper platen and the lower platen, and a soft material is adhered on the upper platen surface on the wafer side. The processing apparatus includes the upper platen and the lower platen, and laps both the surfaces of the semiconductor wafer by having the semiconductor wafer disposed between the upper platen and the lower platen, and the processing apparatus has the soft material adhered on the upper platen surface on the wafer side.
Inventors:
MEZAKI, Yoshio (1-1, Koyakita 1-chome, Itami-sh, Hyogo 16, 〒6640016, JP)
目崎 義雄 (〒16 兵庫県伊丹市昆陽北一丁目1番1号 住友電気工業株式会社伊丹製作所内 Hyogo, 〒6640016, JP)
YAMAZAKI, Tetsuya (1-1, Koyakita 1-chome, Itami-sh, Hyogo 16, 〒6640016, JP)
目崎 義雄 (〒16 兵庫県伊丹市昆陽北一丁目1番1号 住友電気工業株式会社伊丹製作所内 Hyogo, 〒6640016, JP)
YAMAZAKI, Tetsuya (1-1, Koyakita 1-chome, Itami-sh, Hyogo 16, 〒6640016, JP)
Application Number:
JP2010/072602
Publication Date:
July 14, 2011
Filing Date:
December 16, 2010
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES,LTD. (5-33, Kitahama 4-chome Chuo-ku, Osaka-sh, Osaka 41, 〒5410041, JP)
住友電気工業株式会社 (〒41 大阪府大阪市中央区北浜四丁目5番33号 Osaka, 〒5410041, JP)
MEZAKI, Yoshio (1-1, Koyakita 1-chome, Itami-sh, Hyogo 16, 〒6640016, JP)
目崎 義雄 (〒16 兵庫県伊丹市昆陽北一丁目1番1号 住友電気工業株式会社伊丹製作所内 Hyogo, 〒6640016, JP)
住友電気工業株式会社 (〒41 大阪府大阪市中央区北浜四丁目5番33号 Osaka, 〒5410041, JP)
MEZAKI, Yoshio (1-1, Koyakita 1-chome, Itami-sh, Hyogo 16, 〒6640016, JP)
目崎 義雄 (〒16 兵庫県伊丹市昆陽北一丁目1番1号 住友電気工業株式会社伊丹製作所内 Hyogo, 〒6640016, JP)
International Classes:
H01L21/304; B24B37/00; B24B37/04
Attorney, Agent or Firm:
NAKATA, Motomi et al. (1-3, Shimaya 1-chome, Konohana-ku, Osaka-sh, Osaka 24, 〒5540024, JP)
Download PDF:
Claims:
Previous Patent: ENCODER, DECODER, AND DATA CONFIGURATION
Next Patent: NETWORK SYSTEM, CONTROLLER, AND NETWORK CONTROL METHOD
Next Patent: NETWORK SYSTEM, CONTROLLER, AND NETWORK CONTROL METHOD
