METHOD, APPARATUS AND RESULTING STRUCTURES IN THE

MANUFACTURE OF SEMICONDUCTORS FIELD OF INVENTION

The present invention relates generally to the manufacture of electronic circuit assemblies and to the fabrication of substrates for electronic circuits and electronic circuit assemblies. It will be convenient to hereinafter describe the invention in relation to the use of a metal substrate to support semiconductive material in the fabrication of integrated circuit devices and in relation to integrated circuit devices fabricated on so-called engineering substrates by way of flip chip mounting. It should be appreciated, however, that the present invention is not limited to that use, only. BACKGROUND ART

Throughout this specification the use of the word "inventor" in singular form may be taken as reference to one (singular) or more than one (plural) inventors of the present invention. The inventor has identified the following related art.

In the manufacture of modern, high density electronic products, it is often advantageous to mount integrated circuits in what is referred to as a "Flip Chip" manner. In this process, unpackaged chips may be mounted face down on circuit boards or other interconnecting substrates. By "face down" it is meant that the active surface, or the side of the chip containing active devices, is positioned against the circuit board or substrate.

Connections between the chips and circuit board may be made using features such as solder bails or "bumps", These balls can be formed on the circuit board but may preferably be formed on the chip itself. To flip-chip mount a device on a circuit board for example, the chip may be positioned, ordinarily by machine, at the correct location on the circuit board and the chip is heated to re- flow the solder balls so they wet to the contacts on the circuit board, thereby forming the electrical connections.

Generally, the term "flip chip" refers to an electronic circuit component or semiconductor device that can be mounted directly onto a substrate, board, or carrier or the like in a "face-down" manner. As the electrical connection may be achieved through conductive bumps or balls built on the surface of the chips, the mounting process is 'face-down ¹ in nature. During the actual mounting, the chip

may be flipped on the substrate, board, or carrier, (hence the name 'flip-chip'), with the bumps being precisely positioned on their target locations. Because flip chip configurations do not require wire bonds, their size is much smaller than their more conventional counterpart arrangements. The flip chip may be structurally different from more traditional semiconductor packages and wire bond arrangements. Accordingly, flip chip mounting requires an assembly process that may also differ from the more conventional semiconductor assembly. Flip chip assembly may comprise predominantly three major steps: 1 ) bumping of the chips; 2) 'face-down' attachment of the bumped chips to the substrate or board; and 3) under-filling, which is a process of filling the spaces between the chip and the substrate or board with a non-conductive but mechanically protective material.

Flip chip mounted devices may offer several advantages, comprising the following: • Chips do not necessarily need to be packaged, which may provide a cost saving;

• Interconnections between chip and circuit board may be relatively short which is advantageous in high frequency circuits where inductance of interconnections can adversely affect performance; • High density interconnection may be possible.

However, the inventor has recognised there are problems with the above form of flip chip circuit assembly and mounting, and these may be summarised, as follows:

• Since chips may be separated from the circuit board or substrate by the solder balls, thermal management of the chip may be difficult.

Heat may need to be extracted through the balls themselves or through separate structures which may be arranged in physical contact with the chips. This additional structure may detract from the efficiencies gained in the first place by mounting bare chips on the circuit board in flip chip fashion.

• Unpackaged chips may be mechanically fragile and stresses which can exist between the circuit board and chip may be coupled into

the chip by the rigid solder balls, and this may potentially cause the chips to fracture and fail. This may be particularly true of chips made from compound semiconductors such as Gallium Arsenide (GaAs) and Indium Phosphide (InP), which are generally less robust than Silicon (Si) based chips.

• It may also be possible that during the flip chip mounting process, certain circumstances may prevail that lead to the solder balls shifting out of the desired contact positions. Examples of these circumstances may comprise inadvertent movement of one or both of the chip and the board possibly by way of an environmental disturbance during a solder re-flow or, the effect of differences in the coefficient of thermal expansion between the chip, the board or any intermediary material structure.

Further examples of the problems that may be associated with flip chip mounting and attempts at alleviating them are described in the following patent literature, the disclosures of which are incorporated herein by reference.

US Patent No. 7,015,066 (Tsao et al), assigned to Taiwan Semiconductor

Manufacturing Co. Ltd, which discloses a method of re-straining a substrate to reduce overall stress in a flip chip mounted assembly. US Patent Application No. 10/807,220 (Houle et a!), assigned to Intel Corporation published as US

2004/0173897, which discloses a heat spreader arrangement for a flip chip assembly having down set legs and a notch within the heat spreader. US Patent

Application No. 10/707,609 (Chen et al) published as US 2004/0124540, which discloses a method and apparatus in which first and second bumps and corresponding holes are positioned within respective bump and hole positioning areas for maintaining alignment of the assembly components.

The inventor has also recognised that in order to obtain economies of scale and consequently lower the costs associated with fabrication of semiconductor circuits and devices, semiconductor manufacturers desire the use of ever larger semiconductive wafers. Silicon crystal boules may be readily grown to accommodate 12 inch diameter wafers. However, many industries are using compound semiconductor devices fabricated from materials such as, for example, gallium arsenide, indium phosphide and, gallium nitride. Devices and circuits

made from these materials are, however, relatively expensive compared to those made from silicon semiconductors. As one example of the differences between silicon and compound semiconductor materials, compound semiconductor wafers are more brittle and prone to damage than conventional single crystal silicon wafers. Furthermore, wafers of compound semiconductors typically have maximum diameters of, for example, six inches, four inches and two inches for gallium arsenide, indium phosphide and, gallium nitride, respectively.

The inventor further recognises that conventional processing techniques for fabricating semiconductor chips may comprise the following steps, for example: i. Grow epitaxial device layers on mono-crystalline substrate; ii. Conduct 'front end' process step(s), for example, pattern these layers and other deposited dielectric and metallic layers using photolithographic techniques; iii. Bond wafers face down to a temporary supporting substrate after the front end process is complete; iv. Thin wafers by mechanical grinding or lapping the back side; v. Create 'via' holes in the substrate to provide means for connecting the back side ground to appropriate front side ground connections; vi. Deposit metai film on the wafer's back side to provide a ground plane and coat walls of via holes to make contact with the front side ground connections; vii. Dice wafers into individual chips.

In particular, the inventor recognises that most commercial manufacturing facilities presently are geared to providing at least steps i) to iii) noted above.

Considerable investment may be made in establishing and qualifying these above noted front end processes in foundries and any improvements in methods and processes may need to be balanced against this cost. In addition, new processes for manufacturing semiconductor devices and circuits should take into account the inherent limitations of existing facilities.

Certain advances in semiconductor manufacturing techniques have been provided by the inventor as disclosed in US patents 6,919,261 and 6,960,490 in the name of the present applicant and these are incorporated herein by

reference. These patents describe a method of manufacturing semiconductor devices on wafers using examples of composite substrates.

Any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or before the priority date of the disclosure and claims herein. SUMMARY OF INVENTION

It is an object of the present invention to provide a method, apparatus and devices, which alleviate at least one disadvantage associated with related art arrangements as discussed herein.

In one aspect, an embodiment of the present invention provides a method of fabricating an electronic circuit comprising the steps of: providing a composite substrate assembly which comprises a second substrate portion forming a back face of the assembly bonded to a semiconductor wafer portion comprising at least one electronic device and forming a front face of the assembly such that the bonding provides a mechanical support for and in electrical contact with the wafer portion and a relationship between the coefficient of thermal expansion of the second substrate and the wafer portion that alleviates thermal stresses in the wafer portion; mounting the composite substrate assembly onto a first substrate such that the front face of the assembly is in operative connection with the first substrate.

In another aspect, an embodiment of the present invention provides a method of dissipating heat from an electronic circuit arrangement comprising the steps of: operatively associating a first substrate with a composite substrate assembly comprising a semiconductor wafer portion and a second substrate portion wherein the second substrate is adapted for conducting heat away from the wafer portion. In a further aspect, an embodiment of the present invention provides a method of aligning an active face of a composite substrate assembly with a first substrate, the composite substrate assembly comprising a second substrate

forming a back face of the assembly and a semiconductor wafer portion forming the active face, the method comprising the steps of: providing at least one via structure disposed from the active face towards the back face; referencing the composite substrate assembly with the first substrate by guiding conductive fastening means associated with the first substrate into contact with the at least one via structure,

In yet another aspect, an embodiment of the present invention provides a semiconductor device assembly comprising: a composite substrate assembly comprising a second substrate portion and a semiconductor wafer portion wherein; the composite substrate assembly is mounted onto a first substrate such that a front face of the semiconductor wafer portion is in operative connection with the first substrate. In still another aspect, an embodiment of the present invention provides a method of fabricating an electronic circuit comprising the steps of: providing a composite substrate assembly wherein the composite substrate comprises a second substrate portion forming a back face of the assembly and a semiconductor wafer portion forming a front face of the assembly; mounting the composite substrate assembly onto a first substrate such that the front face of the assembly is in operative connection with the first substrate.

In essence, embodiments described above stem from the realisation that a semiconductor wafer manufactured on a second substrate thereby forming an engineered substrate as described herein provides increased support for a flip chip mounted semiconductor as well as increased thermal conductivity to spread heat from the active face of the device and a means by which via structures may be readily formed in the assembly to facilitate self alignment of the chip to the first substrate. The above noted embodiments of the present invention have been found to result in a number of advantages, such as:

Integrated circuit devices assemblies may be provided which combine the electrical properties of the semiconductor wafer with the mechanical, electrical

and thermal characteristics of the second substrate to yield robust, high performance devices with improved thermal characteristics;

The embodiments provide a means of mounting high power RF chips, such as power amplifiers, in a way which reduces interconnect inductance, and improves thermal characteristics.

In one other aspect, an embodiment of the present invention provides a method of manufacturing a composite substrate suitable for use in fabricating electronic circuits comprising the steps of: providing a first semiconductor wafer comprising at least one semiconductor device layer; forming portions of semiconductor devices on a front side of the semiconductor wafer, performing at least one further action comprising one or more of: a) at least one thinning process step for thinning the first semiconductor wafer; b) at least one bonding process step for bonding the first semiconductor wafer to a complimentary surface; and forming additional circuit features on the front side of the bonded semiconductor wafer. In another aspect, a further embodiment of the present invention provides a method of manufacturing a composite substrate suitable for use in fabricating electronic circuits comprising the steps of: providing a first semiconductive substrate comprising at least one semiconductor device layer; forming portions of semiconductor devices on a front side of the semiconductive substrate; performing at least one further action comprising one or more of: c) at least one thinning process step for thinning the first semiconductive substrate; d) at least one bonding process step for bonding the first semiconductive substrate to a complimentary surface; wherein the step of performing at least one further action is conducted in accordance with at least one predetermined criteria.

In further processing steps thereafter, preferred embodiments may provide for forming additional portions of semiconductor devices on the front side of the semiconductive substrate.

In yet another aspect, an embodiment of the present invention provides a method of manufacturing a composite substrate for use in fabricating electronic circuits comprising the steps of: providing a second substrate; forming at least one second alignment feature on the second substrate; providing a first semiconductive substrate comprising at least one semiconductor device layer and at least one first alignment feature thereon; aligning the second and first substrates with reference to the second and first alignment features; referencing subsequent fabrication process steps in accordance with the alignment features. In essence, embodiments described above stem from the realisation that delaying one or more of thinning and bonding steps may allow improved manufacturing processes related to the fabrication of engineered substrates compatible with conventional fabrication processes of foundries and accordingly eliminate cost barrier entry for such engineered substrates. .In one example, a preferred embodiment of the present invention makes use of existing fabrication equipment by way of alignment means to make use of the advantages of composite engineered substrates.

It is envisaged that embodiments as described herein may be carried out with a computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing electronic circuits, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing any one or more of the method steps as disclosed herein.

Products of the method and process steps described herein may be produced by way of apparatus adapted for manufacturing electronic circuits, said apparatus comprising:

processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform any one or more of the method steps as disclosed herein. The presently described embodiments have been found to result in a number of advantages, such as:

Wafer bonded engineered substrates may be adopted with a minimised cost of adoption.

Simplified manufacturing processes may be realised. Improved yield in circuit manufacture under existing fabrication processes by providing benefits of compound substrates that provide improved thermal performance and convenience of via and trench structures.

Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. DESCRIPTION OF DRAWINGS

Further disclosure, objects, advantages and aspects of the present application may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are given by way of illustration only, and thus are not limiting to the scope of the present invention, and in which:

Figure 1 shows a conventional flip chip mounting assembly; Figure 2 shows an arrangement incorporating a composite substrate assembly in a flip chip mounted arrangement on a printed circuit board in accordance with a preferred embodiment of the present invention;

Figure 3 shows an arrangement incorporating a composite substrate assembly in a flip chip mounted arrangement on a printed circuit board in accordance with a preferred embodiment of the present invention and further illustrates the flow of heat through the arrangement; Figure 4 is a flow chart illustrating related art method steps in the fabrication of electronic circuits in which front end processing has been delayed in an overall manufacturing process;

Figure 5 is a flow chart illustrating method steps in the fabrication of electronic circuits in accordance with a preferred embodiment of the present invention;

Figure 6 is a plan view of a substrate for use in bonding with a compound semiconductive wafer showing alignment features in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION With reference to the accompanying drawings, figure 1 shows a flip chip mounted IC device according to related art as identified by the inventor in a conventional manner. Flip chip 102 is mounted on circuit board 100 containing circuit interconnection means 101 as would be recognised by the person skilled in the art. Connection from the flip chip 102 to the circuit board is made through heat conductive fastening means such as solder balls 105. Flip chip 102 has a thickness indicated by arrows 104 typically in the range of about 200μm to about θ25μm. Solder balls 105 are typically sized between about 50 and about 200μm in diameter. This thickness range may also correspond to other heat conductive fastening means as would be recognised by the person skilled in the art, such as for example solder bumps or points.

Figure 2 (not drawn to scale) shows flip chip 202 mounted according to a preferred embodiment of the present invention incorporating a composite substrate assembly 203. The semiconductor wafer portion 203a of the flip chip composite substrate assembly is mounted against a first substrate comprising the circuit board 200 making contact with circuit connections 201 through solder balls 205 such that the front face of the assembly at the wafer portion 203a is in operative connection with the first substrate. The operative connection is adapted to provide on or a combination of a thermal, an electrical and a mechanical

connection between the wafer portion of the composite substrate assembly and the first substrate. The first substrate may comprise one or a combination of: a substantially ceramic substrate; a substantially semiconductive substrate; a substantially insulating substrate; a substrate comprising metallic portions; a printed circuit board; or a carrier. The semiconductor wafer portion 203a of the composite substrate assembly preferably has thickness indicated by arrows 204a in the range of about 10μm to about 100μm. The second substrate portion 203b of the composite substrate preferably has thickness indicated by arrows 204b of dimensions in the range of about 100μm to about 400μm. The second substrate portion 203b may comprise a substantially semiconductive substrate but is preferably a metal substrate,

Figure 3 shows heat flow indicated by arrows 307 from active electronic device 306 on the front side or face of the semiconductor portion 303a of the composite substrate assembly. Heat is preferentially directed from the active electronic device through the semiconductor portion 303a to the second substrate 303b. The heat may then spread laterally and flow down to circuit board 300 through solder balls 305. Comparing the relative thicknesses of wafer material between that of conventional flip chip 102 in figure 1 to the wafer of figures 2 or 3, it is readily apparent that via structures may be formed as described below. US patents 6,919,261 and 6,960,490 in the name of the present applicant are incorporated herein by reference. These patents describe a method of manufacturing semiconductor devices on wafers using examples of composite substrates, which may be referred to as 'engineered substrates'. For the purposes of this disclosure, an engineered substrate may be defined as a composite substrate assembly comprising a combination of a semiconductor wafer which is bonded to a substrate structure in which the bonded combination provides a resilient mechanical supporting structure for and in electrical contact with the semiconductor wafer and a relationship between the coefficient of thermal expansion of both the semiconductor wafer and the substrate structure that alleviates thermal stresses in the semiconductor wafer. It is to be noted the substrate structure may comprise a semiconductive substrate but is preferably a metallic substrate. Engineered substrates are designed to combine the electrical properties of the semiconductor wafer with the mechanical, electrical and thermal

characteristics of the combined substrate structure to yield robust, high performance devices with improved thermal characteristics.

The present embodiments result from utilising the improved properties of devices made on engineered substrates in a way which overcomes the problems recognised by the inventor that are associated with mounting devices in a flip chip fashion.

Accordingly, embodiments of the present invention provide a method of manufacture for electronic circuit assemblies wherein a semiconductor device fabricated on an engineered substrate is flip chip mounted onto a circuit board assembly. More specifically, embodiments of the invention provide a means of mounting the likes of high power RF chips, such as power amplifiers, in a way which reduces interconnect inductance, and improves thermal characteristics.

In a preferred embodiment the present invention provides a method and means of providing an assembly that may in one form act as a heat sink for an integrated circuit arrangement as shown illustrating heat flow in Figure 3. By way of connecting a composite substrate assembly to a first substrate, for example, a printed circuit board with heat conducting contacts (for example solder balls) such that the backplane of the composite substrate assembly comprises a substantially conductive, preferably metal, substrate such that the heat generated on the semiconductor wafer portion of the composite substrate assembly may be conducted and distributed via the metal substrate. This arrangement may help dissipate heat from devices formed on the front side of the composite substrate assembly by acting as a heat spreader which distributes heat laterally and then through heat conductive fastenings such as solder balls to the underlying structure.

With the above in mind this embodiment of the present invention provides a method of dissipating heat from an integrated circuit arrangement comprising the steps of: operatively associating a first substrate with a composite substrate assembly comprising a semiconductor wafer portion and a metal substrate portion supporting the wafer portion wherein the metal substrate is adapted for conducting heat away from the wafer portion.

The step of operatively associating may comprise connecting the composite substrate assembly to the first substrate by heat conductive fastening means and as noted above, the heat conductive fastening means may comprise soldering points, bails, bumps or the (ike. The first substrate may comprise one of a substantially ceramic substrate; a printed circuit board; a carrier, or the like as well as generally, a substantially semiconductive substrate, a substantially insulating substrate or a substrate that comprises metal or metal portions.

Preferably, the semiconductor wafer portion and the second substrate portion of the composite substrate assembly comprise respective thicknesses of between about 10 and about 100μm

Ordinarily, wafers that are flip chip mounted are subjected to significant mechanical stresses and therefore wafers are not thinned to maximise their ^' mechanical strength. Typical GaAs wafers mounted in this way may be about 625um thick. This means that it is impractical to etch via holes through the full thickness wafers and accordingly all ground connections need to be provided on the front side of the wafer. This makes circuit design difficult and in genera) prevents the use of ground planes which improve device performance. In order to provide a ground plane on the back of a flip chip design assembly, some manufacturers partially thin wafers to say about 200um which is a compromise that provides some benefits for mechanical strength and the ability to fabricate front to back via holes, although with significant difficulty. The inventor recognises this compromise is far from optimal

In accordance with embodiments of the present invention, via holes/structures can readily be made in composite substrates assemblies as described herein because the semiconductor wafer can be made very thin. The mechanical strength required of the wafer may be provided by the associated second substrate, preferably a metallic substrate. in accordance with embodiments of the present invention, vias may be incorporated into wafers from front side to back side as described in the above referenced US patent numbers, US 6,919,261 and US 6,960,490. These embodiments allow mechanically robust devices to be mounted as flip chips without the need for distributing ground connections on the front side of the chip, thereby easing circuit layout restrictions

and improving RF performance. In addition, because vias are made from front side toward second substrate, It is possible to locate a solder ball inside a via hole feature so that a very low inductance connection is made directly from the second substrate to the first substrate on which the flip chip is mounted, Because the solder ball is in physical contact with the second substrate, heat transfer through the ball is also optimised such that the operative connection between the first substrate and the composite substrate assembly may be provided by way of the vias. In a preferred embodiment, the front face of the composite substrate assembly may be separated into individual semiconductor chips prior to it being mounted to the first substrate,

In addition, in the case where solder balls are formed first on the substrate on which the flip chip is mounted and then reflowed to mount the chip, it is advantageous to co-locate the solder balls with via holes on the flip chip so that the chip tends to self align during the mounting process. This provides a means of aligning the composite substrate assembly with the first substrate by engaging the solder balls with the via structures as a guide means.

In the above referenced US patents a method was disclosed involving steps of bonding metal substrates to compound semiconductor wafers with attainable benefits being, amongst others, better thermal performance from increased thermal conductivity and the ability to design front side via trenches of any size or shape depending on the requirements of the device itself. In certain embodiments disclosed therein it was envisaged that thinning and bonding would be undertaken prior to any front end processing, as shown in figure 4. From the perspective of cost reduction this may be an optimum process flow since the semiconductor wafer has the lowest cost at this point and therefore the lowest scrap value should wafers be broken at thinning given that a value adding front end processing has not occurred at this point.

Nonetheless, the inventor recognizes that this method may potentially require a common industry front side process to be modified thereby creating a cost barrier to adoption. These cost barriers may be caused by chemical incompatibility, for example, a damaging interaction between wet etching and the metal substrate; equipment related, for example, achieving requisite flatness with respect to lithographic yields; or even compatibly with other process steps within

a foundry, for example, cross contamination such as the danger of copper Cu being present in the system for subsequent processing of non-bonded wafers. Although the inventor considers that these problems may be overcome in time, the inventor has identified that they may represent a significant impediment to the initial adoption of the engineered substrate technology by commercial foundries. .

However, the inventor has now further realised that it is possible to define a process where the semiconductor wafer is thinned and bonded after the front end process has commenced and before the back end process is started.

Accordingly, in one embodiment there is provided a composite substrate fabrication process comprising the steps of: providing a first semiconductor wafer comprising at least one semiconductor device layer; forming portions of semiconductor devices on a front side of the semiconductor wafer; performing at least one further action comprising one or a combination of:

• at ieast one thinning process step for thinning the first semiconductor wafer;

• at least one bonding process step for bonding the first semiconductor wafer to a complimentary surface; and forming additional circuit features on the front side of the bonded semiconductor wafer.

Preferably, the additional circuit features may comprise one or more of: metal interconnect and; via hole features. In another preferred embodiment there is provided a method of manufacturing a composite substrate suitable for use in fabricating electronic circuits comprising the steps of: providing a first semiconductive substrate comprising at least one semiconductor device layer; forming portions of semiconductor devices on a front side of the semiconductive substrate; performing at least one further action comprising one or a combination of:

• at least one thinning process step for thinning the first semiconductive substrate;

• at least one bonding process step for bonding the first semiconductive substrate to a complimentary surface; wherein the step of performing at least one further action is conducted in accordance with at least one predetermined criteria.

The step of performing at least one further action may comprise: temporarily bonding the first wafer or substrate for thinning; thinning the first wafer or substrate; subsequently bonding the first wafer or substrate to the complimentary surface.

The back end process may comprise actions such as any of steps iv), v) or vi) as noted in the conventional processing techniques noted above and may comprise the addition of dielectric, via etching and metal deposition as outlined in figure 5, and as would be recognised by the person skilled in the art. The resultant method of manufacture is a method by which the technical performance benefits available from wafer bonding to produce engineered substrates can be obtained with the lowest cost of adoption. Here cost of adoption refers to how much change would be required to adapt an already existing process in order for a semiconductor-metal composite to be processed.

The decision as to where in the fabrication process the thinning & bonding step(s) may be inserted is one dependent on predetermined criteria comprising one or a combination of the following:

• Has all wet chemistry been completed • Are the active components on the surface well protected,

• Is the surface mechanically strong

• Is the uppermost processed surface conducive to wafer mounting for thinning

• Is the topology of the wafer surface conducive to achieving accurately thinned wafer

With respect to the uppermost or outermost processed surface being conducive to wafer mounting for thinning, this principally refers to the chemical nature of the part processed wafer ie is the uppermost surface dielectric, or metal.

As an example, the processing of a heterojunction bipolar transistor (HBT) wafer could be paused at the layer called 1 ^st metal, with the wafer then being temporarily bonded for the purpose of thinning and then subsequently bonded, using the above method, to a metal substrate as previously described in the case of an engineered substrate. In this case, 1 ^st metal would be recognised by the person skilled in the art as a process step as being the first metal layer used to provide broad area connectivity between devices on the wafer. At this point the wafer may well be protected by underlying dielectrics and the partially metalised surface may provide good adhesion during thinning.

It is important to note that in this embodiment, bonding of a metal substrate to compound semiconductor wafers part way through a process flow may be used in many other instances. For each of these applications the breakpoint at which thinning and bonding to the engineered substrate is inserted would be determined on a case by case basis, with attention to the requirements of the predetermined criteria listed above.

In accordance with a preferred embodiment of the present invention a bonding process is now described with reference to the use of a metal substrate as the "second" substrate in the overall form of an engineered substrate.

As described in US' patent numbers 6,919,261 and 6,960,490 assigned to the present applicant the metal substrate may be prepared by depositing an inert coating layer on the back of the metallic substrate to reduce the risk of interaction between the metal substrate and processing chemistry. A thin layer (typically less than 1 μm in thickness) of a noble metal such as gold or platinum is generally suitable for this purpose, providing it is also compatible with equipment and processes intended to be employed in subsequent steps. Preferably, the coating is non-reactive with subsequent semiconductor processing steps. Other materials (such as silicon nitride) can also be used, provided such materials have sufficient resistance to process chemistry and temperatures used in the intended wafer processing steps.

The bonding layer is deposited on the front surface of the metallic substrate. This metallic bonding layer is preferably made from two or more metals that form a eutectic alloy on heating. The outermost layer is preferably a noble metal (such as gold) that prevents the underlying layers from oxidising before and during bonding. Underlying layers may be formed of tin or indium. These metals are chosen such that the eutectic alloy forms at relatively low temperature (for example, 200 Degrees Celsius) and having formed, has a re- melt temperature in excess of any temperature encountered during wafer processing. The bonding layer may also serve as an inert coating layer for the metallic substrate'.

A complementary bonding layer may also be deposited on the back-side of each thinned semiconductor wafer. This complementary bonding layer is also preferably metallic and its composition is chosen to provide maximum adhesion to the semiconductor over the range of subsequent processing temperatures. The preferred layer structures may comprise the following: titanium/gold or titanium/platinum/gold, but many other combinations of metals are possible without departing from the scope and spirit of the invention.

Numerous other bonding layer compositions are possible, and may be chosen to match particular processing requirements (such as maximum temperature) of different semiconductor materials. For example, it may be advantageous to form the preferred indium bonding layer on the semiconductor wafer instead of the metal substrate. The advantage may come from simplifying the manufacturing processes used to produce the metal substrate and hence reducing overall costs. In this case, the metal substrate's gold passivation layer may also serve as the bonding layer. Non-metallic complementary bonding layers, for example, such as silicon, polysilicon, silicon dioxide or silicon nitride may also be used.

In a preferred embodiment, a metallic substrate materia! is chosen as the second substrate to match the coefficient of thermal expansion (CTE) of the chosen semiconductor over the required range of processing temperatures. The substrate material is also chosen for its strength, thermal and electrical conductivity and cost. Preferably, the substrate also has a high thermal conductivity to carry away heat from an integrated device formed thereon.

According to certain embodiments, the thermal conductivity of the metallic substrate may be 165 Watts/m-Kelvin or greater.

For example, an alloy of approximately 90% tungsten and 10% copper matches the CTE of gallium arsenide and has suitable electrical and thermal conductivity. The metallic substrate is preferably made as thin as possible so as not to increase the weight or heat capacity of the composite structure. A typical thickness might be in the range of about 150 to about 300 μm. An advantage of using a metallic substrate is that the CTE can be adjusted by changing the composition of the metal alloy. No such adjustment is possible if a crystalline substrate such as silicon is used.

In yet a further embodiment of the present invention there is provided a method of manufacturing semiconductor wafers using composite substrates, for example, as described herein, where the second (preferably metal) substrate is shaped to provide alignment features, for example, flats and these fiats may be aligned to corresponding flats on a semiconductive wafer. This alignment may take place at any suitable stage in the fabrication process, however, it is preferable that this occurs during bonding and, furthermore, it is preferable that the flats are such that industry standard fabrication equipment may be operatively associated with the resultant composite substrate so as to use these flats as a means for referencing in processing the composite substrate after bonding. This beneficially provides an alignment reference for subsequent processing steps after bonding with optimal cost benefit.

The flatness of the metallic substrate may be specified particularly if the composite pair is to be processed with any lithographic steps. The preferred metal substrate may include major and/or minor flats along one edge as shown in Figure 6. These flats are then aligned to the corresponding flats on the semiconductor wafer so that wafer processing equipment utilizing a "flat finder" can maintain correct orientation of the composite substrate. The dimensions and location of these flats should according to the inventor follow industry standard substrate conventions.

For purposes of this disclosure, including the appended claims, the term "integrated circuit" shall be defined as a combination of interconnected circuit

elements inseparably associated on or within a continuous substrate. For purposes of this disclosure, including the appended claims, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, comprising, but not limited to, bulk semiconductive materials such as semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). For purposes of this disclosure, including the appended -claims, the term "substrate" refers to any supporting structure, comprising, but not limited to, the semiconductive substrates described above.

While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth.

As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the specific embodiments are to be understood to be illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-plus-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures.

"Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof."