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Title:
METHOD AND APPARATUS FOR SIMULTANEOUS PROPAGATION OF MULTIPLE CLOCK FREQUENCIES IN SERIALIZER/DESERIALIZER (SERDES) MACROs
Document Type and Number:
WIPO Patent Application WO/2021/047370
Kind Code:
A1
Abstract:
The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f 1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f 2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f 1 and the common mode encoding the second high-speed clock frequency f 2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.

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WO/2009/142557METHODS AND AN APPARATUS FOR ESTIMATING A RESIDUAL FREQUENCY ERROR IN A COMMUNICATIONS SYSTEM
Inventors:
LACROIX MARC-ANDRE (CA)
MOHSENPOUR MOHAMMADMAHDI (CA)
Application Number:
PCT/CN2020/110331
Publication Date:
March 18, 2021
Filing Date:
August 20, 2020
Export Citation:
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Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H04L7/033
Domestic Patent References:
WO2008058256A22008-05-15
Foreign References:
US10749663B12020-08-18
US20090134923A12009-05-28
US9654123B12017-05-16
US20150091617A12015-04-02
US20040153894A12004-08-05
US20090239559A12009-09-24
US20110037759A12011-02-17
US20090134923A12009-05-28
Other References:
See also references of EP 4022836A4
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