METHOD AND APPARATUS FOR TOKEN TRIGGERED MULTITHREADING

WIPO Patent Application WO2004034340

A3

Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used. The processor may be configured so as to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads, without introducing blocking conditions leading to thread stalls.

WO/2008/073005	MODULAR ENGINEERING SYSTEM
JP3988144	Vector processing device and overtaking control circuit
JPS60220425	CONTROL SYSTEM OF CONSOLE WORK STATION

HOKENEK ERDEM
MOUDGILL MAYAN
GLOSSNER JOHN C

PCT/US2003/031905

August 26, 2004

October 09, 2003

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SANDBRIDGE TECHNOLOGIES INC (US)

G06F9/00; G06F9/30; G06F9/312; G06F9/38; G06F9/54; G07F9/00; G07F; (IPC1-7): G07F9/00

US5613114A	1997-03-18
US5339415A	1994-08-16
US6151683A	2000-11-21
US6341338B1	2002-01-22
US5742840A	1998-04-21
US5404469A	1995-04-04

See also references of EP 1550089A4

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