Power supply overload protection refers to the attempt to keep regardless of the ex- ternal load the internal losses of an electric power supply so small that the tem- perature rise will not damage the power supply. Protection is realized by somehow limiting the current fed by the supply. A known protection arrangement against overload is schematically illustrated in Fig. 1. A power supply comprises a feeding unit 11 and a regulator 10. The feeding unit 11 and at the same time the whole power supply is in this case a d. c. supply. The feeding unit 11 comprises an a. c. source and a rectifier, for example. The regulator 10 comprises a regulating element 12, control unit 14, current-sensing element 15 and a voltage-sensing element 16, placed in series with the load. Electric energy thus comes from the feeding unit 11 and is conducted via the regulating element 12 to the load 13. A'load'means in this context a loading impedance the resistive part of which is R. The magnitude of the loading caused by the load on the supply, mainly on the regulating element in the regulator, is indicated by the power dissipation Ph of the regulating element. The regulating element 12 is preferably realized by means of one or more semiconductor elements. The resistance of the regulating element 12 can be adjusted and/or it can be switched into a conductive and non-conductive state. The regulating element may be a bipolar transistor the base current of which and, hence, the current through the transistor is variable. Signal S 1 proportional to the load current I is brought to the control unit 14 which uses it to control the regulating element as necessary. The voltage of the feeding unit 11 is Vi and that of the load 13 is Vo. The difference of these two, Vj-VO= AV, equals the voltage across the regulating element 12. The power dissipation Ph is then the product AV-1. Normally the regulating element 12 is also used for continuous adjustment of the load voltage Vo, whereby signal S2 pro- portional to voltage Vo is also brought to the control unit 14.

From the prior art it is known several methods to provide protection against an overload. These methods are below described, referring to Figs. 1,2 and 3. Fig. 2 shows the load voltage Vo as a function of current I in different cases, and Fig. 3 shows the power dissipation Ph of the regulating element as a function of the load resistance R, in the corresponding cases.

In the current limiting procedure the regulating element 12 is controlled such that the load current I will not rise above a predetermined value Im no matter how small <BR> <BR> <BR> the load resistance F4. So, the load current is limited. Plot 21 in Fig. 2 illustrates this procedure. A disadvantage of the procedure is that power dissipation Ph increases as the resistance R) goes below R, m which is the lower limit of the normal fluctuation range of the load resistance. Power dissipation is high especially in a short circuit situation, i. e. when the resistance Rl is nearly zero. This is illustrated by plot 31 in Fig. 3.

In foldback short circuit protection the regulating element is controlled such that the load current I decreases from value Im to a relatively small value Is as the load re- sistance Ra goes from the lowest normal value Rlm to zero. Plot 22 in Fig. 2 repre- sents this method. This way, power dissipation in a short circuit condition will not be so high as to be harmful. Instead, the problem is, as illustrated by plot 32, that in a partial short circuit the power dissipation Ph at certain values of the load resistance Rt may rise so high that at least the regulating element is destroyed. A certain non- linear load may also have the same effect.

In cut-back short circuit protection the regulating element 12 is driven suddenly non-conductive as the load exceeds a certain limit, represented by point A in Fig. 2.

Plot 23 illustrates this method. In the area marked by the broken line the state of the regulator is unstable so that as the load increases the plot goes after point A straight back to the origin. Thus the power dissipation Ph in a short circuit and in partial short circuit is very small, as shown by plot 33 in Fig. 3. A disadvantage of the method is that once the overload has been removed the regulator will not automati- cally start up without an auxiliary arrangement which results in costs.

A protection method developed from the above cut-back method utilizes pulse con- trol. As the load exceeds a certain limit corresponding to resistance Rlr and current 1,, the regulating element is first driven non-conductive. Then it is driven periodi- cally conductive with a relatively low pulse ratio, i. e. for relatively short periods of time. The load situation is sensed during these relatively short ON periods. If an overload no longer exists, the regulator will return to normal operation. In addition to the current limit Ir that triggers the pulse control, known circuits also have a second, higher current limit Im that limits the short circuit current during pulses. The method has no significant disadvantages. Costs of the arrangement and a consider- able power dissipation in spite of the pulse control in a short circuit situation can be regarded as relative disadvantages. Plot 34 illustrates losses Ph corresponding to pulse control as a function of the load resistance Ri.

In a temperature limiting protection method the regulating element is driven non- conductive as the temperature of the regulator exceeds a certain limit. This is real- ized using a signal from a temperature sensor in the circuit. A drawback of the method is the slowness of operation: the protection starts only after the overload has lasted for a relatively long time, and the return to the normal mode after the over- load has ceased may take a relatively long time. Another disadvantage is that the protection arrangement results in relatively high costs.

An object of the invention is to eliminate the aforementioned disadvantages relating to the prior art. The method according to the invention is characterized by what is expressed in claim 1. The arrangement according to the invention is characterized by what is expressed in claim 4. Preferred embodiments of the invention are pre- sented in the dependent claims.

The basic idea of the invention is as follows. A source of electricity comprises a d. c. supply and a regulator. The load current is controlled by the regulator and a regu- lating element in it. An upper limit value, or maximum allowable current, is defined for the load current. The regulator continuously senses the current fed by the source to the load. Loading is monitored. When an overload is detected the load current is forced substantially to zero and at the same time the regulator is set to pulse control mode. In pulse control mode, current pulses are fed to the load at regular intervals.

The current value of the current pulses is limited to the maximum current mentioned above. The load current is sensed during the pulses just as in normal operation.

When it is detected that the current is smaller than said maximum current, the pulse control mode is terminated and operation returns to normal.

An overload is defined as a condition in which the load current exceeds the upper limit value for a predetermined period of time. An overload is detected by monitor- ing the load current and comparing it to said upper limit value or, alternatively, on the basis of the load voltage level; an overload is detected as the load voltage drops below a certain lower limit value for a predetermined period of time.

An advantage of the invention is that the power dissipation of the supply in a short circuit situation is small, smaller than in known regulators employing pulse control type protection. This can be attributed to the use of one current limit instead of two.

Another advantage of the invention is that the power dissipation is small also in a partial short circuit situation, at all load resistance values and also with other types of load, such as reactive and nonlinear loads. A further advantage of the invention is that the regulator returns with certainty to normal operation once the overload has

been removed. A yet further advantage of the invention is that the overload protec- tion comes on and off quickly compared to protection based on temperature. Yet another advantage of the invention is that when applied to the short circuit protec- tion of an auxiliary output of a relatively high-power supply, the losses caused by the protection in a normal situation remain relatively low. Still another advantage of the invention is that one and the same circuit is used both to start the pulse control and to limit the current, which means cost savings.

The invention is below described in detail. Reference is made to the accompanying drawing in which Fig. 1 is a block diagram of an overload-protected power supply, Fig. 2 shows loading curves of known power supplies, Fig. 3 shows power dissipation curves of known power supplies, Fig. 4 shows a regulator with an arrangement according to the invention, Fig. 5 illustrates the operation of the arrangement according to the invention, Fig. 6 shows the power dissipation curve of a regulator with the arrangement according to the invention, Fig. 7 shows a second regulator with a second arrangement according to the invention, and Fig. 8 shows a third regulator with a third arrangement according to the inven- tion.

Figs. 1,2 and 3 were already discussed in conjunction with the description of the prior art.

Fig. 4 shows a regulator 40 employing an arrangement according to the invention for preventing an overload in a d. c. power supply. An unstabilized d. c. voltage Vi is brought to the regulator 40 in Fig. 4. The regulating element 42 in this embodiment is a power field-effect transistor, hereinafter called a FET. The channel conductivity <BR> <BR> of the FET gets better as the gate voltage V4 drops. Direct current is fed to a load 43 through the regulator 40. In parallel with the load 43 there is a capacitor Cl for fil- tering the voltage and preventing oscillation.

The regulator 40 includes a control unit 44. The control unit 44 comprises a regu- lating unit 444 for the output voltage as well as for the load voltage Vo. The regu- lating unit 444 is realized using an amplifier A3. A sensing element 46 for the load voltage Vo is comprised of resistors R9 and R10 connected in series, and a voltage v8 proportional to voltage Vo is taken from between said resistors and brought to the

non-inverting input of amplifier A3. To the inverting input of amplifier A3 it is brought a constant voltage Vref generated by means of a zener diode ZD. The zener <BR> <BR> <BR> ZD gets most of its current via resistor Rl 1 from the output of the regulator. To start the regulator the zener ZD gets a small current via resistor R12 from the regulator <BR> <BR> <BR> input IN. Amplifier A3 is connected to the gate G of the FET 42 via resistor R13.

Thus the regulating unit 444 controls the FET 42 during normal operation. As the voltage Vo drops a little as the load increases, for example, voltage v8 drops, too. <BR> <BR> <BR> <P>Then amplifier A3 forces the gate voltage V4 low, causing the load current I to grow until voltage Vo again reaches its nominal value (l+R9/R10)-Vref.

The control unit 44 in the regulator 40 in Fig. 4 uses an arrangement for preventing <BR> <BR> <BR> an overload. The arrangement comprises a constant current generator 441, amplifier unit 442 and a pulse generator 443. The arrangement also includes a current-sensing <BR> <BR> <BR> element 45 in series with the FET 42, realized in this case by resistor R1. This ar- rangement realizes the limitation of the load current I in overload conditions.

The constant current generator 441 is in this embodiment implemented using two transistors Ql and Q2. The constant current generator 441 generates a constant cur- rent I1 0.7V/R7 which is independent of the variation of the input voltage Vj.

The amplifier unit 442 is in this embodiment implemented using a first amplifier Al. The output of the amplifier unit 442 and first amplifier Al is connected to the gate G of the FET 42 via diode D1. The non-inverting input of amplifier A1 is con- <BR> <BR> <BR> nected between resistors R2 and R4. One end of resistor R2 is connected to the<BR> <BR> <BR> <BR> <BR> <BR> upper-voltage end of resistor RI, i. e. regulator input IN, and one end of resistor R4 is connected to the constant current generator 441. The inverting input of the first <BR> <BR> <BR> amplifier Al is connected between resistors R3 and R5. One end of resistor R3 is connected to the lower-voltage end of the current-sensing element 45, i. e. current- <BR> <BR> <BR> measuring resistor Rl, and one end of resistor R5 is connected together with resistor R4 to the current generator 441. The circuit is designed such that as the current I stays within its normal fluctuation range, the voltage vl of the inverting input of the first amplifier A1 is greater than the voltage v2 of the non-inverting input. The out- put voltage V3 of amplifier A1 is then low and the first diode D1 operates in the re- verse direction and, therefore, amplifier A1 does not affect the operation of the FET 42. As the current I grows, the voltage drop of the current-sensing element 45, or resistor R1, increases and, consequently, voltage vl drops. Once voltage vi reaches voltage V2 the output voltage vs of amplifier A1 goes high, the first diode D1 be- <BR> <BR> <BR> comes conductive, and the gate voltage V4 also goes high, closing the channel of the FET 42. If the resistances of resistors R4 and R5 are equal, the resistance of resistor

R2 must be a little higher than that of resistor R3. The current I is then limited to value ImaX-Il- (R2-R3)/(2-Rl), maintaining the equilibrium mentioned above.

The pulse generator 443 is in this embodiment realized by means of a second ampli- fier A2. The non-inverting input of the second amplifier is connected via resistor R15 to the operating voltage Vi, via resistor R16 to the operating voltage-5V, and via resistor R14 to the output of the second amplifier A2. The voltage v6 of the non- <BR> <BR> <BR> inverting input depends on these connections: as the output voltage V7 of the second amplifier A2 is high, voltage v6 gets its upper value v6,, and as voltage v is low, voltage v6 gets its lower value v6a. Between the inverting input and output of the second amplifier A2 there is a first series connection of resistor R17 and fourth diode D4 in parallel with a second series connection of resistor R18 and fifth diode D5. The fourth and fifth diodes D4 and D5 are connected to the output of the second amplifier A2 in opposite directions. In addition, the inverting input is connected via capacitor C3 to voltage-5V. As the pulse generator 443 is in operation and the out- <BR> <BR> <BR> put voltage V7 is high the second amplifier A2 charges capacitor C3 via resistor R17 until the voltage vs of the inverting input reaches the value v6y. At that point voltage V7 suddenly drops to its lower value near voltage-5V. Subsequently the second amplifier A2 receives current as capacitor C3 discharges via resistor R18 until volt- age v5 reaches the lower limit value V6a. At that point output voltage V7 suddenly rises to its upper value near the operating voltage Vi. The operation thus goes on cyclically. The output of the first amplifier Al is connected via the second diode D2 to the inverting input of the second amplifier A2, and the output of the second am- plifier A2 is connected via the third diode D3 to the inverting input of the first am- plifier A 1.

The lower operating voltage of the first amplifier A1 in the amplifier unit 442 is-5V <BR> <BR> <BR> which means the output voltage V3 is below zero when the load current I is within its normal range. The second diode D2 is then conductive and the first amplifier A1 prevents the pulse generator 443 from oscillating: voltage v5 is continuously nega- <BR> <BR> <BR> tive and voltage v7 is continuously high. The third diode D3 thus operates in the reverse direction and the second amplifier A2 does not affect the operation of the amplifier unit 442. As the current I reaches the value Ima, voltage v3 goes up, the second diode D2 becomes non-conductive and capacitor C3 starts to charge up via resistor R17. The first charging cycle, Tr in Fig. 5, is relatively long since voltage Vs <BR> <BR> is at first low, near-5V. Once voltage v5 reaches the value v6y, voltage v7 drops.

The third diode D3 then becomes conductive, pulling voltage v, down. Voltage Vs <BR> <BR> <BR> goes up and raises the gate voltage V4 of the FET 42 close to voltage Vs which also

is the voltage of the source S of the FET. The FET 42 thus becomes non-conductive and the load current I drops substantially to zero. Components C3 and R17 thus form a time constant circuit which for its part determines how quickly the regulator reacts to the load current value Imax. The operation of the pulse generator 443 then <BR> <BR> continues cyclically. Always when the output voltage V7 of the pulse generator 443 is low, the third diode D3 is conductive and the load current I is forced to zero. Al- <BR> <BR> ways when the output voltage v7 of the pulse generator 443 is high, the third diode D3 is non-conductive and the first amplifier Al allows the current I to rise to said value ImaX. If the overload has disappeared, the current I will not rise all the way up to ImaX whereby voltage vi will not drop to v2. Voltage Vs will then go negative in- stead of settling to the level corresponding to current ImaX. The second diode D2 be- comes conductive, preventing the pulse generator 443 from oscillating. The regula- tor 40 returns to normal operation. In accordance with the description above an overload is detected on the basis of the fact that the load current I rises to Imax and stays there for a predetermined period of time. The transition to and from the pulse control of the load current is realized using the second diode D2 and third diode D3.

The actual pulse control is determined in the pulse generator 443 and the magnitude of the load current I by the current generator 441, amplifier unit 442 and current- sensing element 45.

Fig. 5a illustrates the variation of the load current I and Fig. 5b that of the load voltage Vo in a regulator according to Fig. 4. Moments tl, t2 and t3 are marked on the time axis t. Prior to moment tl the loading is normal: Current I varies in accor- dance with the load and voltage Vo stays at its nominal value Von. At moment tl the load impedance suddenly drops to a value corresponding to an overload. The load is then an overload. The third amplifier A3 in the regulating unit 444 quickly increases the load current I until the current reaches the limit value ImaX. The load voltage V. in turn drops to a value Vol = Imax'R) corresponding to the resistance R, of the over- load. After moment t, the voltage V5 of capacitor C3 starts to rise as described above. When time Tr has passed, the regulator is considered to be in an overload condition. Then follows the closing of the regulating element, i. e. FET 42, which was discussed above, whereby both current I and voltage Vo drop substantially to zero. After that, the pulse generator 443 operates in cycles, and current pulses Pi are conducted into the load 43. The regulator is then in a state that corresponds to an overload. The cycle length T equals the sum of the charge and discharge times of capacitor C3 in the pulse generator 443. Resistance R18 is an order of magnitude greater than resistance R17. Therefore, the charge time of capacitor C3 is an order of magnitude shorter than the discharge time and, correspondingly, the length of a

current pulse Pi is an order of magnitude smaller than the cycle time T. With a pulse ratio like this the average power dissipation Ph of the regulating element remains relatively small.

At moment t2 in the example of Fig. 5 the regulator is practically short-circuited.

This has no effect on the magnitude of current pulses Pi, but voltage pulses Pv natu- rally drop to nearly zero. At moment t3 the overload is removed, i. e. the load returns <BR> <BR> <BR> to normal. The next time that the output voltage V7 of the pulse generator 443 goes high, the load voltage Vo rises to its nominal value Von, whereby the regulator aban- dons the state corresponding to an overload and returns to normal mode.

Fig. 6 shows power dissipation curves for regulators equipped with overload pro- tection based on pulse control. Plot 61 represents the losses of a known regulator utilizing two current limits, and plot 62 represents the losses of a regulator accord- ing to the invention utilizing one current limit. As the load resistance Rl drops to value Ri, corresponding to the overload limit, or value Ir of current I, the power dis- sipation in both cases at first increases to a certain limit Phmax and then drops to a small fraction of it as the pulse control is started. As the load resistance further decreases from value Rlr, losses occur during the current pulses. In a regulator using two current limits the losses at first increase as current I increases and the voltage AV of the regulating element 12 remains unchanged (cf. Fig. 1). As the load resis- tance Rl drops towards zero from value Rlm corresponding to the second current limit Im, the rate of increase of the losses grows as the voltage difference AV grows, even though current I is no more growing. In a short circuit the power dissipation is Phi = d-Vi Im, where d is the pulse ratio. In a regulator according to the invention the losses grow steadily as the load resistance decreases from Rir to zero. In a short <BR> <BR> <BR> circuit the power dissipation is Ph2 z d-Vj-Ir. This is clearly smaller than Phl as cur- rent Ir is in practice e. g. 3/4 of current Im.

Fig. 7 shows a regulator 70 with an arrangement according to the invention for pre- venting an overload. This arrangement is realized in such manner that an overload is detected by sensing the voltage Vo of the load 73. Otherwise the regulator and the protection against an overload are in this embodiment arranged as in Fig. 4. The regulator 70 includes a FET 72 as a regulating element. The control unit 74 com- prises a constant current generator 741, amplifier unit 742 and a pulse generator 743, which correspond to the respective units 441,442 and 443 in the control unit of Fig. 4. The current-sensing unit 75 is in this embodiment, too, implemented using a resistor R1 and corresponds to the current-sensing unit 45 in Fig. 4. A regulating unit 744 controls the output voltage Vo like the regulating unit 444 in Fig. 4.

Additionally the overload prevention arrangement of regulator 70 in Fig. 7 com- prises a comparator unit 745 which now, instead of the amplifier unit 442 of regu- lator 40 in Fig. 4, switches the pulse generator 743 (443) on and off. The compara- tor unit 745 includes a comparator A4 and resistors R20 and R21. Resistors R20 and R21 are connected in series over a zener diode ZD so that the constant voltage Vr2 between the resistors is smaller than the voltage Vref of the zener diode. Voltage Vr2 is connected to the non-inverting input of comparator A4. The sensing element 76 for the voltage Vo of the load 73 comprises resistors R9 and R10 connected in series, and the voltage v8 between said resistors, which is proportional to voltage VOX is conducted to the non-inverting input of the third amplifier A3 in the regulat- ing unit 744. The same voltage Vg proportional to the load voltage Vo is connected to the inverting input of the comparator A4. The output voltage V9 of the comparator <BR> <BR> A4 is connected via diode D2 to the pulse generator 743 just like voltage V3 in the regulator of Fig. 4. As an overload causes voltage Vo to drop substantially from its nominal value Von, voltage v8 becomes smaller than voltage vr2 whereby the output voltage vg of the comparator A4 goes to its higher value, enabling the operation of the pulse generator 743. Using an arrangement based on the comparator unit 745 it is possible to select a voltage limit at which the pulse control is started: if continu- ous current supply is desired with slight overloading, the resistances of resistors R20 and R21 are chosen such that voltage vr2 is clearly smaller than voltage vref.

Fig. 8 shows a regulator 80 which, too, is equipped with an arrangement according to the invention for preventing an overload. The source from which the regulator 80 and load 83 are fed is in this case a high-power d. c. supply. Thus the input IN repre- sents an auxiliary output of a relatively high-power d. c. supply used to feed more than one device. Regulator 80 differs from regulator 40 of Fig. 4 in that the voltage- regulating unit 444 and diode Dl have been removed as unnecessary. Regulator 80 comprises a FET 82 as a regulating element, and resistor Rl as a current-sensing element 85. A constant current generator 841 and amplifier unit 842 correspond in their structure and operation to the respective units 441 and 442 of Fig. 4. During normal operation, the output voltage v3 of a first amplifier Al of the amplifier unit 842 is low, as in the regulator of Fig. 4. As the first diode D1 has been removed, the first amplifier Al now drives the FET 82 fully conductive, whereby the load voltage Vo is nearly the same as the voltage Vi of the feeding source. Because of the small voltage difference, the losses caused by the protection remain low with a normal load. If a predetermined current limit is exceeded, pulse control is started and only relatively short current pulses Imax of a limited magnitude are fed into the load 83, as

in Fig. 5. The feeding source avoids a major increase of load in a short circuit situation.

Above it was described examples of overload protection according to the invention.

The invention is not limited to the circuit arrangements described. The inventional idea may be applied in many different ways within the scope of the invention as defined by the claims appended hereto.