TECHNICAL FIELD

The present disclosure relates to a method of cell selection in a Modular Multilevel Converter (MMC). BACKGROUND

A modulation operation of MMC control is shown in figure l. The modulating signal (reference voltage) is obtained from the P-Q controller. Phase shifted carrier (PSC) based Pulse- Width Modulation (PWM) is used for a modulator. Cell capacitor voltages are balanced by adding or subtracting an in-phase component of the current with the reference voltage. Corresponding control hardware configuration is shown in figure 2a and the control block diagram of a cell voltage controller is shown in figure 2b. The cell voltage controller is located in the Cell Control Unit (CCU) of figure 2a.

SUMMARY

It is an objective of the present invention to provide cell selection in an MMC which results in more even use of the cells.

A modulation operation comprising cell selection is shown in figure 3. An advantage of using such control architecture is to allow use of advanced PWM schemes like Space Vector Modulation (SVM), Flux Tolerance Band (FTB) modulation, flux average modulation, etc., to operate the converter around fundamental switching frequencies (i.e. Pulse Number, PN = 2). These PWM techniques operate at low switching frequencies and still generates reduced lower order harmonics. This reduces or eliminates the need for lower order harmonic filters resulting in significant cost savings. The PWM for all the three phases are generated in the centralized processing control board. This control board mainly decides whether a cell has to be inserted or bypassed in each of the phases at any given time. The PWM information of the respective phases is passed on to the control hub where the sorting algorithm is placed. The sorting algorithm decides on the most suitable cell that can be inserted or bypassed among the available cells. The information of all the cell capacitor voltages per phase is available in one control hub. This allows to use a different method (called a sorting algorithm) to select appropriate cell for capacitor voltage balance.

A cell may be selected based on capacitor voltage, which is known as voltage- sorting (i.e., conventional sorting). The cells are arranged (in an array) in ascending fashion according to the capacitor voltage. The required number of cells are chosen either from the beginning or from the end of the array based on the charging/discharging cycle and the modes (insert/bypass) of operation. A flow-chart for a conventional sorting algorithm is shown in figure 4.

To observe the performance of voltage-sorting at very low pulse number (PN=2) i.e., fundamental switching frequencies, a flux average based PWM was simulated. The results focus on the cell voltage and loss distribution among the cells of a converter phase leg (say phase-AB, considering delta connected StatCom). The cell capacitor voltages for voltage-sorting at low pulse number (around fundamental) were observed to deviate much from the average voltage at the lower region. During inductive mode of operation the cell capacitor voltages deviate much from the average voltage at the upper region. The peak to peak ripple was calculated from the difference of maximum cell voltage in inductive case and minimum cell voltage in capacitive case, which was found to be 31% for the considered cell

capacitance.

The switching and conduction losses of the semiconductor devices (e.g.

switches (optionally including diodes), herein referred to as "devices") in the cells were calculated (using information of switching pulse and device parameters) to compute the net cell level losses. The cell level losses for all the cells in a phase leg was monitored to identify the deviation in losses between the cells. It was seen that the conventional sorting algorithm produces a large cell level loss deviation. Some cells had a loss of 140% whereas other cells had a loss of only 60%. This indicates that the loss distribution among the cells is uneven with a conventional sorting algorithm when operating around fundamental switching frequencies. This results in uneven aging/wear of the cells, or the devices therein, and increased cooling requirements. Thus, a problem with using conventional sorting at a low pulse number is that there is a wide range of losses and of how many switching operations each cell performs during a time period, why the cells age at different speeds due to unequal wear. This gives the need to develop a sorting algorithm that can select cells not only based on the cell capacitor voltage, but also on the losses incurred in the cell (e.g. total losses in the cell which can be called cell-level losses, or losses for individual semiconductor devices in the cell which can be called device-level losses). Losses may be a combination of switching losses and conduction losses and may be calculated in a

conventional way.

As mentioned above, the cell capacitor voltage balance may be achieved by voltage-sorting. However, the losses may not be evenly distributed among the cells of a phase leg e.g. when operating at fundamental switching frequencies. In accordance with the present invention, the deviation of losses among the cells can be reduced when the cells are sorted by considering their losses as well.

According to an aspect of the present invention, there is provided a method of cell selection in an MMC connected to an AC grid and comprising a plurality of phase-legs each comprising a plurality of series connected converter cells each of which comprising an energy storage. The method comprises, for each of the phase-legs: obtaining information about a voltage of the energy storage of each of the plurality of cells; obtaining a switching command for the phase- leg; obtaining information about losses in each of the plurality of cells;

assigning a cell weight to each of the plurality of cells based on the obtained voltage information and obtained loss information; selecting which of the plurality of cells to insert or bypass based on the obtained switching command and on the assigned cell weights; sending firing signals to the plurality of cells in accordance with the cell selection; and calculating losses in each of the plurality of cells. According to another aspect of the present invention, there is provided a computer program product comprising computer-executable components for causing a controller to perform an embodiment of the method of the present disclosure when the computer-executable components are run on processing circuitry comprised in the controller.

According to another aspect of the present invention, there is provided a controller configured for controlling a power converter. The controller comprises processing circuitry, and storage storing instructions executable by said processing circuitry whereby said controller is operative to for each phase-leg of an MMC: obtain information about a voltage of the energy storage of each of the plurality of cells; obtain a switching command for the phase-leg; obtain information about losses in each of the plurality of cells; assign a cell weight (W _ce ii) to each of the plurality of cells based on the obtained voltage information and obtained loss information; select which of the plurality of cells to insert or bypass based on the obtained switching command and on the assigned cell weights; sending firing signals to the plurality of cells in accordance with the cell selection; and calculating losses in each of the plurality of cells.

According to the present invention, focus is given to distribute the phase-leg level stored energy equally between the cells, ensuring more equal loss distribution. In comparison with the conventional sorting algorithm, the cells are sorted according to a weightage assigned to each cell. The individual cell weightage may be calculated based on the weightage function for cell capacitor voltage deviation from its nominal as well as on the loss

experienced by the cell. The cell with the highest weightage may then be used for the switching operation. No weightage may be given to reduce the lower order harmonics or Total Harmonic Distortion (THD) since they are taken care by the modulation. In addition to this, an upper limit may be imposed on the cell capacitor voltage, such that no cell exceeds the specified limit. A control algorithm may be used which optimizes between the cell capacitor voltage ripple and loss distribution between the cells in a phase leg. A heuristic sorting algorithm may use weightage functions for cell capacitor voltage and losses incurred by cells to identify a suitable cell to be selected to be used for switching operation (inserted/bypassed).

It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings. Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first", "second" etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

Fig 1 is a schematic block diagram of an embodiment of modulator control logic of prior art.

Fig 2a is a schematic block diagram of an embodiment of control hardware of prior art.

Fig 2b is a schematic block diagram of an embodiment of a cell voltage controller of prior art. Fig 3 is a schematic flow chart of an embodiment of modulator control logic in accordance with the present invention.

Fig 4 is a schematic flow chart of an embodiment of a sorting algorithm of prior art. Fig 5a is a schematic block diagram of an embodiment of an MMC in star (wye) configuration, in accordance with the present invention.

Fig 5b is a schematic block diagram of an embodiment of an MMC in delta configuration, in accordance with the present invention.

Fig 6 is a schematic diagram of an embodiment of a bipolar converter cell in accordance with the present invention.

Fig 7 is a schematic block diagram of an embodiment of control hardware in accordance with the present invention.

Fig 8a is a schematic graph illustrating an embodiment of a weight function for voltage balance during a cell insert operation, in accordance with the present invention.

Fig 8b is a schematic graph illustrating an embodiment of a weight function for voltage balance during a cell bypass operation, in accordance with the present invention.

Fig 9 is a schematic graph illustrating an embodiment of a weight function for voltage balance during loss distribution, in accordance with the present invention.

Fig 10 is a schematic flow chart of an embodiment of a method of the present invention.

DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description. Figures 5a and 5b illustrate two different types of MMC 1, in star (wye) and delta configurations, respectively, with which embodiments of the present invention may beneficially be used. Other embodiments of the present invention may be used for any other converter topology comprising cascaded chain-linked cells in series and/or parallel, such as HVDC or FACTS converters. Each converter 1 comprises three phase-legs 2, each which a plurality of series connected cells 3. The converters of figures 5a and 5b, respectively, represents star (wye, Y) and delta topology examples and may be connected within a three-phase AC grid, for balancing the phases therein, and may e.g. be a StatCom. The MMC 1 also comprises a controller 10 which is schematically shown in figure 5a. The controller may be a control system comprising a central unit and/or distributed units associated with respective legs or branches 2. The controller 10 may be configured, e.g. by means of computer software, to perform embodiments of the method of the present disclosure. The converter cells 3 may be any type of conventional MMC cell, such as a type of unipolar (half-bridge) or bipolar (full-bridge, H-bridge) cell. The invention does not require the cells to be bipolar, why at least one, some or all of the cells 3 of each phase-leg 2 may in some embodiments of the invention be unipolar cells. Different types of unipolar and bipolar cells are well-known in the art.

Figure 6 illustrates an example of a bipolar cell 3. The cell comprises an energy storing device 5, here in the form of a capacitor. The capacitor 5 may give rise to voltage ripples, which may be compensated for. The energy storing device 5 may comprise a capacitor arrangement with any number of capacitors in series and/or parallel connection with each other. The cell 3 also comprises four semiconductor switches S, forming the full-bridge (H-bridge) topology in the cell. Similarly, a corresponding unipolar cell 3 comprises only two semiconductor switches S, forming a half-bridge topology. Any number of semiconductor switches may be used, and the cell with four switches shown in the figure is only an example. The semiconductor switches of the bipolar cell are conventionally named in the figure as Si switch, S2 switch, S3 switch and S4 switch. When the switches Si and S4 are closed and S2 and S3 are open, the cell is in a +1 state in which a positive voltage will be applied. By opening Si and S4 switches and closing S2 and S3 switches, this voltage is reversed whereby the cell is in a -1 state and a negative voltage will be applied. Zero voltage (cell bypass), the cell being in a o state, may be obtained in two different ways, by closing the upper switches Si and S3 (lower switches S2 and S4 being open) or by closing lower switches S2 and S4 (upper switches Si and S3 being open). A switching command to a bipolar cell 3, from the controller 10, may be either an insert command or a bypass command. In case of an insert command, the cell is inserted to produce either positive by closing switches Si and S4, or negative voltage by closing switches S2 and S3. In case of a bypass command, either the switches Si and S3 (o state type 1) or the switches S2 and S4 (o state type 2) are closed.

Regardless of whether a bipolar or unipolar cell is used, each of the S switches may comprise e.g. an insulated-gate bipolar transistor (IGBT) or a gate commutated thyristor GCT (in which case a snubber circuit may also be needed), for instance an integrated gate commutated thyristor (IGCT), a reverse-conducting IGCT (RC-IGCT) or a bi-mode GCT (BGCT), possibly in combination with an antiparallel one-direction conducting/blocking component such as a diode. In the example of figure 6, each S switch comprises an IGCT and antiparallel diode.

Embodiments of the present invention may be especially advantageous for cells 3 having a relatively low switching frequency, e.g. of at most 125 Hz, e.g. at most 100 Hz or 50 Hz. In some embodiments, the cells of the MMC has a switching frequency equal to or about the nominal fundamental frequency of a three-phase AC grid, e.g. 50 Hz or 60 Hz.

Figure 7 illustrates an embodiment of control hardware of an MMC controller 10. A main controller or control unit 71 produces a voltage reference U _re f for each of the three phases on which PWM is employed by a processing unit 72 To produce a cell insert or bypass switching command for each of the phase legs 2. A control hub 73 for each phase (here called 73a, 73b and 73c) performs the sorting algorithm for cell selection whereby the n cells which are to receive the switching command are selected. The respective CCU 74 of the selected cells 3 then sends firing signals to the semiconductor switches (valves) S in accordance with the switching command. The Uci to U _cn in figure 7 blocks 73a and 74 represent that the cell capacitor voltages are sensed and sent to those blocks. U _C i represents the sensed cell capacitor voltage of the first cell etc. Figure 7 may be related to the flow chart of figure 3 in that the main modulating signal U _re f of figure 3 may be produced by the main control unit 71, the PWM may be performed by the centralized processor 72, and the cell selection is performed in the decentralized control hubs 73.

In accordance with the present invention, a cell selection method may be used which assigns weightage with is a function of both cell capacitor voltage deviation from its nominal and loss experienced by the cells to identify the suitable cell for switching. The new sorting algorithm is herein named heuristic sorting. The valve losses may be distributed equally among the cells 3 (or the devices S1-S4 in the cells) in a phase leg 2 with embodiments of the present invention. The maximum cell capacitor voltage may also be kept within the specified limit. The developed sorting algorithm may be used along with a PWM technique (e.g. FTB based PWM) which operates at low pulse number (e.g. PN about 2). The pulse number of the converter may be chosen to be about 2 (i.e., fundamental device switching frequency) in which case the problem of loss distribution between the cells 3 and capacitor 5 voltage balancing is magnified. The heuristic sorting algorithm may sort the cells 3 based on the weightage assigned to the cells. The cell with the highest weightage will then be selected for cell insert/bypass operation. Two types of expressions to define the cell weightage for heuristic sorting algorithm are presented as examples.

According to Type-I heuristic sorting, the cell level weight (W _ce ii) may be expressed through equation 1. On the other hand, W _ce ii for Type-II heuristic sorting may be expressed through equation 2.

Type-i: W _cell = W _vb * W _u (1) Type-2: W _cell = W _vb + W _ld (2) where,

Wceii is the weightage given to each cell for inserting and bypassing operation,

Wvb is the weightage function for the cell voltage balancing,

Wid is the weightage function for the cell loss distribution.

The cell weightage W _ce ii is thus a function of both the voltage balancing and, in accordance with the present invention, of the loss distribution.

The weight (W _v b) for voltage balance as a function of cell capacitor 5 voltage (Vceii) during charging and discharging of a cell 3, for cell insert operation, may be expressed using equation 3 and equation 4, respectively:

G 1 V dc,n - V cell CX vb - ^{~ ~} \ ) °Ί ^{_ (j} 2

V - G V

w = -^a ^{2 DC} ' ^N (A)

G _L - G ₂ where,

Vceii is the individual sensed cell capacitor voltage,

Vdc,n is the nominal cell capacitor voltage, Gi and G2 are the gains of the weightage function for voltage balancing.

The Gains Gi and G2 are tuned based on a trial and error method. For the MMC 1 considered, the values of Gi and G2 may e.g. be chosen as 2 and o respectively. For a cell bypass operation, the weight of the cell 3 for voltage balance during charging may be calculated using equation 4 and during discharging using equation 3. A weight function for voltage balance (W _v b) during charging/discharging condition, for a cell insert operation is illustrated in figure 8 a and for cell bypass operation in figure 8b.

Typically, the cells 3 may operate between 0.9 Vdc,n and 1.1 Vdc,n, but the weightage function is defined over the region for cell voltages between o to 2 Vdc,n for the considered case. Based on the sensed cell capacitor voltages and the current polarity (charging or discharging), the cell weightage for voltage balancing follows the functions defined above. If the cells are sorted based on the weightage assigned only from the cell voltage balance, conceptually the technique may be similar to a conventional sorting algorithm.

An example weight function for loss distribution (Wid) during

charging/discharging operation and cell Insert/Bypass command is expressed in equation 5.

W _u (5) where,

Gi is the loss optimization gain, and Lceii is the loss deviation.

The switching and conduction losses of the semiconductor devices S in the cells 3 are calculated using information of switching command and device parameters. The sum of semiconductor losses and any clamp losses, etc., may be summed to compute the cell-level losses of each cell. The cell-level loss may then be integrated over time. The aim may be to distribute this cell-loss- integral value equally over time among all the cells 3. The least value of the cell-loss-integral, among all the cells, at any instant of time, may be subtracted from the cell-loss-integral of all cells in a phase leg to ensure the cell-loss-integral is always zero for the cell which the least combined historical losses. The thus modified cell-loss-integral may be denoted as the Cell Loss deviation (L _ce ii). Put another way, the loss (L _ce ii) of a cell may be calculated as the combined historical loss of that cell relative to the cell in the same phase-leg having the lowest combined historical losses. A weight function for loss distribution is illustrated in figure 9. The flowchart of figure 10 illustrates embodiments of heuristic sorting in accordance with the present invention. According to this embodiment, the cell level weights are calculated according to either equation 1 or equation 2. The cells are then sorted in a descending fashion based on their weights. The cell with the highest weight is chosen for the next switching operation. If the cell capacitor voltage of any cell passes above a threshold voltage, that cell may be bypassed regardless of its weightage and another cell whose voltage is below the threshold may be inserted instead. Note that the conventional (or voltage) sorting algorithm may be triggered if the cell voltage of any cell 3 passes above a threshold voltage, to reduce the peak overvoltage of the cells. In a first step 101, the weights W _ce ii for each of the cells 3 in a phase-leg 2 are calculated for charging/discharging and Insert/Bypass commands. Then, in step 102, it is determined whether the cell capacitor voltage of any cell is above a predetermined threshold voltage. If no cell capacitor voltage is above the threshold, the cells 3 are sorted in step 106 based on descending order of cell weights W _ce ii. The cells 3 used for the switching (insert/bypass) operation are then selected in step 107.

If at least one cell has a cell capacitor voltage which is above the threshold voltage, it is (in step 103) determined whether there is a sufficient number of cells 3 available to replace the at least one cell. If there is, the at least one cell is bypassed in step 104 and the insert command counter is incremented by one or by the number of bypassed cells. Then conventional voltage sorting may be performed in step 105. If there is not, conventional voltage sorting of step 105 may be performed on the cells 3 including the at least one cell which exceeds the threshold voltage.

The same MMC model as in the Background section was simulated with similar operating condition to test and compare the efficiency of

embodiments of the heuristic sorting algorithm of the present invention compared with a conventional sorting method. The simulated StatCom is first operated in the capacitive mode. When comparing, it was observed that the peaking of cell voltages towards the bottom of the ripple curve was

significantly reduced. Simulating for both capacitive and inductive cases, the cell capacitor ripple was found to be reduced by 20% for Type-I sorting on comparison with the conventional sorting algorithm. For Type-II sorting the cell capacitor ripple was found to be reduced by 10%. For both types, the distribution of losses among the different cells 3 in a phase-leg 2 was also significantly improved (with more even loss distribution).

The simulation results show better voltage balancing in Type-I and better loss distribution in Type-II. The gains may be be tuned accordingly to achieve similar output for both types. The heuristic sorting algorithm thus helps in selecting the cells for switching in such a way that the cell capacitor voltage distribution and loss distribution among the cells 3 in a phase leg 2 are more optimal. Simulations studies were performed with flux average PWM and Heuristic sorting as the cell selection method. No significant

change/distortion in the harmonic spectrum (especially in the lower order) was observed. Embodiments of the present invention may be used to select the cells in an MMC when the desired switching frequency of the converter is low, e.g.

around fundamental switching frequency. PWM techniques like flux average, FTB, etc., may be used to operate the MMC around fundamental switching frequency and still generate low or no undesired lower order harmonics. When operating at such low pulse numbers, there may occur problems with cell capacitor voltage balancing and loss distribution among cells. Heuristic sorting method may be used as the cell selection method along with the flux average, FTB PWM method to solve this problem.

Figure 11 is a schematic flow-chart of an embodiment of the method of the present invention. The method is for cell selection in an MMC 1 connected to an AC grid and comprising a plurality of phase-legs 2. Each phase-leg 2 comprises a plurality of series connected converter cells 3. Each of the plurality of cells 3 comprises an energy storage 5, typically comprising a capacitor. The method may be performed periodically, e.g. every time a switching command is produced. The method may be performed in the control hub 73 of the phase-leg 2, which control hub 73 receives the switching command from the PWM processor 72.

The method comprises, for each of the plurality of phase-legs 2, obtaining Mi information about a voltage of the energy storage 5. The voltage may be measured over a capacitor of the energy storage 5 of the cell. In some embodiments, the obtaining Ml information about a voltage comprises calculating a voltage balance weight (W _V b) for each cell (3).

The method also comprises obtaining (M2) a switching command for the phase-leg 2. The switching command may, as discussed in relation to figure 7, be obtained by being determined by the centralized processor 72 by means of PWM and sent to the control hub 73 of the phase-leg. The switching command includes information about whether one or more additional cell(s) 3 of the phase-leg should be inserter, in state +1 or -1, or bypassed. Based on the switching command, the sorting algorithm of the control hub 73 knows for what it should sort the cells (for being inserted or being bypassed). The method also comprises obtaining M3 information about losses in each of the plurality of cells 3. The loss information regards historical losses

(typically both switching and conduction losses) which are calculated (see step M7), e.g. estimated, by conventional means e.g. after completion of each switching operation whereby the periodicity of the calculations correspond to the switching frequency of the converter 1 or the control sampling rate of the control hub. The obtaining M3 of loss information may comprise calculating a loss distribution weight Wid for each cell 3, as discussed above. In some embodiments, the loss distribution weight Wid is calculated in accordance with equation 5. The loss information may be on cell-level, i.e. relate to the total losses (e.g. sum of losses for all switches S) of the cell. Alternatively, the loss information may be on device-level with separate loss information for each switch S (e.g. including its diode or with loss information of its diode provided separately). Thus, in some embodiments, the obtaining M3 loss information comprises obtaining individual loss information for each of the switches S1-S4 in the cell 3, allowing the sorting algorithm to select cell(s) based on device-level losses (e.g. if a certain switch S of a cell is more worn than other switches of the same cell, the cell may be bypassed regardless.

The obtaining Ml of voltage information, the obtaining M2 of the switching command, and the obtaining M3 of loss information may be performed in any order or concurrently.

The method also comprises assigning M4 a cell weight W _ce ii to each of the plurality of cells based on the obtained Mi voltage information and obtained M3 loss information. In some embodiments, the assigning M4 of a cell weight Wceiimay comprise calculating the cell weight as a function of the voltage balance weight (W _v b) and the loss distribution weight (Wid), e.g. in

accordance with equation 1 or equation 2.

The method also comprises, for each of the phase-legs 2, selecting M5 which of the plurality of cells 3 to insert or bypass based on the obtained M2 switching command and on the assigned M4 cell weights. For instance, if the switching command is to insert an additional cell, the currently bypassed cell having a weight which indicates least relative losses (but also taking into account the cell voltage) may be selected M5. Similarly, if the switching command is to bypass an additional cell, the currently inserted cell having a weight which indicates most relative losses (but also taking into account the cell voltage) may be selected M5. As mentioned before, the cell weights may be dependent on cell-level loss information or on device-level loss information. In case of device-level loss information, since there are two ways of bypassing a full-bridge cell 3 (type 1 and type 2), the selecting M5 may in some embodiments comprise, when the switching command indicates that at least one cell should be bypassed, selecting which of the switches (Si and S3 or S2 and S4) of the cell to close based on the individual loss information. In this way, the relative losses of switches S within a cell may also be balanced.

The method also comprises sending M6 firing signals to the plurality of cells in accordance with the cell selection M5. Thus, the cell selection M5 is, in accordance with the present invention, dependent on a cell weight W _ce ii based on cell loss information.

The method also comprises calculating My losses in each of the plurality of cells, typically by means of sensors detecting e.g. voltage(s), current(s) and/or temperature(s) within the cell after a switching operation has been performed based on the sent M6 firing signals. The calculated My losses will then be used as input for the obtaining M3 of loss information the next time the method is performed. The calculating My losses may comprise measuring losses (e.g. both switching and conduction losses) over each of the switches S in the cell. The switches may in this respect include its diode, or the losses over the diode of the switch may be measured and calculated separately. Also, losses in any clamp circuit of the cell may be measured and calculated. If only cell-level loss information is used, the measured losses may be added together to give a calculated cell-level loss, which may be combined with historical losses. Alternatively, if device-level losses are used, device/switch- level losses are calculated, which may be combined with historical losses. Thus, in some embodiments, the calculating My losses comprises calculating conduction and/or switching losses over each switch S1-S4, optionally comprising a diode, in the cell.

In some embodiments of the present invention, the periodicity of the selecting M5 corresponds to a switching frequency which is the same as a nominal fundamental frequency of the AC grid, e.g. 50 or 60 Hz. However, in other embodiments, any frequency may be used. In some embodiments of the present invention, the plurality of converter cells 3 is at most 50 cells, such as between 10 and 30 cells. However, in other embodiments, any number of cells may be used, e.g. up to 200 cells.

In some embodiments of the present invention, the MMC 1 is in delta configuration, e.g. a StatCom, but any other topology such as star or double- star for e.g. HVDC applications, may be used with embodiments of the present invention.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.