The object of the patent is a method to centralize, restructure, optimize and realize the systemtechnical tasks of the PCM-channel units of SCPC/Single Channe.l Per Carrier/ satellite-communication systems, as well as a circuit arrangement to realize prescribed jobs according to the invented method.

The invention can be advantageously used in micro¬ processor-implemented, modular-type SCPC satellite-communica¬ tion systems, which are expandable in terms of qualitativ and quantitativ parameters, and new services. It is known that state-of-art SCPC PCM-channel units are constructed according to the block-diagram of Figure 1., where every distinct block defines not only the system¬ technical job to be done, but represents at the same time also the actual• ealizing circuit element itself. The operation of a state-of-art channel unit can be described according to Figure 1. Seven bit long PCM-coded bytes coming from PCM-coder PCMK are fed through a delay block KE under the control of gates K to shift registers SR, where two 112 bit long datasegments are contructed. Now 16 bit long blocksynchron codes BSZKl and BSZK2 are inserted by means of blocksynchron penerator BSZG. At the front of the catastream this way contructed 40+80=120 bit long preamble EK is also inserted the aid of the preamble generator EKG. At last properly constructed and continuously incoming data- stream is transponated by the PSKA transmitter - according to a prescribed frequency - onto a carrierwawe of the frequency band 52-88 MHZ.

At the receiver-side all these jobs are done in opposite sense, and the beginning of information-bursts is

sensed by a blocksynchron detector BSZD. The datastream, coming from a PSKV receiver in form of dibit-channels is converted into serial form by a parallel/serial converter P/S. By means of a phasea biguity resolver FBH the system resolves the phaseambiguity caused by turns of the carrier- -cross and by change of sequence of the dibit-channels. At last the seven bit long PCM-coded bytes are reconstructed by a PCM-decoder PCMD.

The disadvantage of the above method is that the whole systemtechnical job is split into subtasks, realized by distinct circuit elements without considering the real computing complexity of them, this way using all circuit elements only once and for one special systemtechnical sub- task per sampling period. Because of this the single circuit elements are optimized in vain, the total ^' system is not optimal. Moreover, there is a further disadvantage that the above view allows only SSI- or MSI-type, less intelligent and more expensive realization. It is a further disadvantage that in a system built in this way some intelligent comput- ing elements are not fully exploited with ^" respect to their computing capacity. In such a wired-logic-type structure the system is not flexible enough to accomodate further developments concerning qualitativ and quantitativ parameters or the introduction of new services. The implementation of up-to-date and economical, modular construction and standardis tion principles resulting in easy production and good maitainability are restricted.

The aim of the invention is to provide a new method and circuit arrangement to realize PCM-channel units of SCPC satellite-communitation systems, which results - on restructuring of the whole systemtechnical task - in an optized system.

The task to be solved by the invention is to realize the this way restructured system by such a complex computing capacity, which is based on up-to-date, powerful but low- priced and wide-spread circuit elements. Furthermore the

invented solution meets modern production test and maintenance requirements on an improved level, allows easy use of new developments concerning qualitativ and quantitativ para¬ meters and the introduction of new services, furthermore ensures - thanks to the unified and modular structure of the system - economical and reliable production and maintenance. This means that if a new and more complex service - for example FEC datatransmission - has to be introduced, some new computing elements are to add to the system. This results in a drastic simplification of production, testing and maintaina ility.

The main point of the invention is that the whole systemtechnical task - as a complex job - is optimally restructured and - with the realizing circuit arrangement in mind and in dynamic interaction - segmented into some number of jobs to be run simultaneously - i.e. at the same time - so as to equally occupy and load computing elements of the invented system.

According to the invented method the systemtechnical tasks of a PCM-channel unit are restructured to give some number of disjunct jobs to be run simultaneously - i.e. the same time -, and to each computing element is ordered one and only one job out of each group of jobs, and after finish¬ ing the first job by each computing element out of each group of jobs, the second job of each group of jobs has to be run - simultaneously again - by each computing element, and so on -, until all jobs to be done in a sampling period are ready.

Thus on one hand, the optimal exploitation of the realizing circuit arrangement is ensured, on the other hand, based on the systemtechnical jobs of the PCM-channel unit the number of the computing element needed - in our proposed circuit arrangement the number of microprocessors - can be determined just like the number, type and character of special hardware elements needed, which can be considered

as peripherials of the constructed special computing sturcture constructed this way and which supply an extended computing capacity to do jobs out of the range of one computing element; this way of implementation makes it possible that the computing elements are identical, and

- due to the flexibility, regarding expandability for future services - tools for promoting the production, test and maitenance - for example a display or something else - can easily be accomodated in the system, and the type of the computing elements is not prescribed, thus always the most economical solution can be chosen. Moreover, by increasing the number of computing elements, modifications in qualitativ and/or quantitativ services, conserning even the system- technique itself are also possible.

Figure 1. shows the blockdiagram of a state-of-art PCM channel unit, .

Figure 2. shows the job-segmentation time-diagram

- according to the invented method -, Figure 3. shows the invented circuit arrangement.

An implementation of the invented method is shown in Figure 2., where a sampling interval has- the. duration t=125 ,usec=l/8 kHz. In the exemplary circuit arrangement of Figure 3. there are four computing elements PR0C1...PR0C4. Restructured systemtechnical jobs to be done are, as follows:

a PCM-signal shift-in b PCM-signal shift-out c Frame-organization d Frame-recovery e Adoptive threshold-adjustment f Threshold-detection g SOM/Start Of Message/-detection

h 'Phaseambiguity-resolution j Self-test

i\ t the beginning of a sampling period to each computi element is ordered a group of systemtechnical jobs, and out of them the first one is chosen to be ordered to a computing element that way that to the first computing element is ordered the job a - the PCM-signal shift-in-, to the second computing element is ordered the job b - the PCM-signal shift-out -, to the third one is ordered the job c - the frame-organization -, and to the fourth one is ordered the job d - the frame recovery. Now taking into account the runtime of the systemtechnical jobs a to d, we order a new job to each computing element, forming this way a new second group of jobs to be run after the first group of jobs, and so to the first computing element is ordered the job e - the adoptive threshold-adjustment -, to the ^' second one is ordered the job f - the threshold-detec tion -, to the third one is ordered the job g - the S0M- -detection -, to the fourth the job h - the phaseambiguity- -resolution -, and at last, as the first computing element /PR0C1/ has yet a bit superfluous, i.e. unused computing capacity in this sampling period /see also Figure 2./, the self-test job j can be run by the computing element PR0C1. A possible implementation of the invented circuit arrangement can be seen in Figure 3. The computing capacity SK is composed of computing elements PR0C1...PR0C4, which are connected to each other and to a common address/data/- control bus via connections B1...B4 in accordance with the job-segmentation. The computing elements PR0C1...PR0C4 are controled by an interrupt generator IG via connections II...14. The computing capacity SK communicates through the common address/data/control bus with a memory M, through a port P0RT1 with a switches-displays block KKD , -through a port P0RT2 with a PSK modem PSKM, and through a

port P0RT3 with a PCM-codec PCMKD, as well as with a block¬ synchron detector BSZD. Common units of the SCPC system are connected to a point IN/OUT of the PSK-modem PSKM, while the telephone-line is connected to a second point IN/OUT of the PCM-codec PCMKD. The operation of the invented circuit arrangement can be described, as follows:

From the PCM-codec PCMKD through the port P0RT3 and the connections B9 in-coming seven bit long PCM-coded bytes are written controled by the processors PR0C1 and PR0C2 via the connections B5 into the memory M, where 32 pieces of these bytes - i.e. 224 bits - are formed- into one frame, and completed by a 32 bit long blocksynchron code. The 256 bit long frame in memory M organized this way is transmitted by the processor PR0C3 via the connections B5 to the port P0RT2, and from there - in form of dibit-channels - it is sent to the PSK-modem PSKM. The PSK-modem PSKM transponates the PSK-modulated signal according to a prescribed carrier frequency into the band 52 - 88 MHz for the sake of trans¬ mission to the common units of the SCPC system. In receiving direction the channel unit operates as follows: dibits arriving from the PSK-modem PSKM via the connections PMJ at the port P0RT2 are fed through connections B7 and the common address/data/control bus BUS to the comput¬ ing element PR0C4. The processor PR0C4 - which is communicating with the other processors via the connections

B4 - recovers the proper blocksynchron by means of the block¬ synchron detector BSZD on the base of information coming from the connections PMJ. This way the received information can be written into the memory M, under the control and via the common bus through the connections B5 and the required 224 bit long frame can be recovered. These frames are fed through the connections B2 to the processor PR0C2. The frames are then decoded into seven bit long bytes by the processor PR0C2, some bit-level operations are done and the seven bit long PCM codewords are fed through the connec-

tions B2, the port P0RT3 and the connections PCMJ to the decoder of the PCM codec PCMKD. From here the analog samples - filtered by an internal switched capacitor channel-filter - are led to the analog telephone-line, i.e. to the point IN/OUT of the PCM-codec unit PCMKD. The inter¬ rupt generator IG ensures /the processors PR0C1...PR0C4/ by the means of the connections II...14 that - do not loose inp samples to be processed, and that the processed output samples are fed to the "outer world" yet in time. A further path is supplied, through the connections B6, the port PORTl and the connections V to operate the block of switches- -displays KKD.

The four computing elements PR0C1...PR0C4 are working simultaneously, but the common memory M can be accesed only by one at a time. This way, by the help of the control- and parameter switch-over among the processors - thanks to the job-segmentation - an optimal computing structure, and - thanks to thorough realization considerations, as well as circuit selection - an optimalized channel unit is resulted.