METHOD AND CIRCUIT FOR DRIVING A HALF BRIDGE

Technical field

The present invention relates to a method and a circuit for driving a half bridge.

Background art

One of the factors that come into play in determining the reliability of an electronic module is temperature.

Various techniques are known for measuring the internal temperature of a power device, which are essentially divided into two classes: direct and indirect measurement techniques.

Direct measurement techniques involve opening, that is, the "decapsulation" of the device in such a way as to directly access the active part thereof and measure its temperature. The detection of the temperature can take place with optical methods, such as infrared cameras or optical fibres in the infrared region, or by contact using thermocouples or other sensors.

These techniques are invasive, expensive and difficult to apply on a large scale.

Indirect measurement techniques, on the other hand, are based on the detection of electrical quantities linked to temperature. These electrical quantities, known in the sector with the acronym TSEP ("Thermo-Sensitive Electrical Parameter") are detected outside the device, thus avoiding having to open it.

In the literature there are several TSEPs that can be used to measure the temperature of a device, including:

- the threshold voltage for MOSFET and IGBT

- the drain-source voltage for MOSFET or collector-emitter for BJT or IGBT, with switched-on device;

- the intrinsic gate resistance for isolated gate devices;

- the analysis of some characteristics of the gate current (e.g. the peak) for isolated gate devices;

- the position of the Miller plateau for MOSFETs;

- the drain-source voltage for MOSFET or collector-emitter for BJT and IGBT at a predetermined current level, measured during the turn-off transient (small currents);

- the time profiles of voltage and current during the switching of the device;

- the saturation current.

An overview of TSEPs used for indirect temperature measurement can be found in the scientific article by Y. Avenas, L. Dupont e Z. Khatir, " Temperature Measurement of Power Semiconductor Devices by ThermoSensitive Electrical Parameters — A Review/', IEEE Transactions on Power Electronics, vol. 27, no. 6, pp. 3081 -3092, June 2012, doi: 10.1109/TPEL.2011.2178433.

Beyond the variability of usable TSEPs, the main limitation of indirect techniques is linked to the need to characterize the curve of the chosen TSEP variable. This characterization often requires a controlled temperature environment, so it is not easily feasible on a large scale.

There are also specific limits linked to the particular selected TSEP variable.

The measurement of temperature based on the saturation current is described for example in the scientific article by D. Bergogne, B. Allard and H. Morel, "An estimation method of the channel temperature of power MOS devices", 2000 IEEE 31 st Annual Power Electronics Specialists Conference. Conference Proceedings (Cat. No.00CH37018), Galway, Ireland, 2000, pp. 1594-1599 vol.3, doi: 10.1109/PESC.2000.880543.

The measurement obtained with this technique is affected by a low signal- to-noise ratio, due to the small measurement current (the saturation current is much lower than the collector current during the switched-on state of the IGBT), in turn caused by the work at a fixed gate voltage close to the threshold voltage. From the Italian patent no. 102017000122136 in the name of the Applicant, a method and a circuit for driving an active half bridge comprising two transistors, by forcing one of the two to assume a controlled current generator configuration while the other transistor remains switched-on, are also known.

Disclosure of the invention

In this context, the technical task underpinning the present invention is to provide a method and a circuit for driving a half bridge, which obviate the drawbacks of the prior art cited above.

In particular, the object of the present invention is to propose a method and a circuit for driving a half bridge which allow controlling the dissipated power at single component level in a more granular way with respect to the solution described in the Italian patent no. 102017000122136.

Another object of the present invention is to propose a method and a circuit for driving a half bridge which allow measuring the temperature of a device indirectly with no need for calibration in a controlled environment.

Another object of the present invention is to propose a method and a circuit for driving a half bridge which allow making the measurement of temperature for one or both devices of the half bridge.

Another object of the present invention is to make available a method and a circuit for driving a half bridge which allow measuring the temperature indirectly, achieving a better signal-to-noise ratio with respect to known solutions.

The specified technical task and the specified purposes are substantially achieved by a method for driving a half bridge comprising a first device and a second device, the second device being a transistor, the method comprising the steps of:

- driving the devices with signals in accordance with a periodic modulation pattern configured in such a manner that in a period the first device assumes a switched on configuration for a fraction of period; - forcing the second device in a current generator configuration controlled by a switch-on pulse for an interval of time that is greater than a time constant of the second device, maintaining in the meantime the first device in the switched on configuration;

- adjusting the duration of the interval of time starting from the calculation or prediction of the average power P _avg dissipated over the period, characterized in that it comprises a step of adjusting the amplitude of the switch-on pulse so as to vary the current circulating in the second device.

In accordance with an aspect of the invention, the adjustment of the amplitude of the switch-on pulse is performed as a function of a control signal.

In accordance with one embodiment, the control signal is a digital or analogue modulated signal.

In accordance with one embodiment, the control signal is a PWM signal.

In accordance with an aspect of the invention, the method also comprises the steps of:

- measuring a circulating current value in the second device when it is in the controlled current generator configuration;

- obtaining a temperature value of the second device as a function of the measured current value.

In accordance with an aspect of the invention, the method further comprises a thermal characterization step of the second device so as to establish a relation between the current circulating in the second device and the temperature of the second device.

In accordance with an embodiment, the step of measuring the circulating current value in the second device comprises a step of sampling the current around the centre of the switch-on pulse.

In accordance with an embodiment, the step of measuring the circulating current value in the second device comprises taking a plurality of current samples during the switch-on pulse. In accordance with an embodiment, the second device is a MOSFET transistor so that the switch-on pulse is a voltage pulse between gate and source of the second device.

In accordance with another embodiment, the second device is a BJT transistor, so that the switch-on pulse is a voltage pulse between base and collector of the second device.

In accordance with another embodiment, the second device is an IGBT transistor, so that the switch-on pulse is a voltage pulse between gate and emitter of the second device.

The stated technical task and specified objects are substantially achieved by a circuit for driving a transistor of a half bridge, comprising:

- a first three-state logic gate having an input configured to receive an input signal, a further input configured to receive a first enabling signal and an output;

- a second three-state logic gate having an input configured to receive the input signal, a further input configured to receive a second enabling signal complementary to the first enabling signal such that at each period only one of the three-state logic gates is in a high impedance condition, and an output, wherein the first three-state logic gate is supplied by a first fixed supply voltage and the second three-state logic gate is supplied by a second supply voltage that is variable as a function of a control signal.

In accordance with an aspect of the invention, the driving circuit further comprises an LDO converter that, in response to the control signal is configured to reduce the amplitude of the first supply voltage and to provide as output the second supply voltage.

Brief description of drawings

Further characteristics and advantages of the present invention will become more apparent from the approximate and thus non-limiting description of a preferred, but not exclusive, embodiment of a method and of a circuit for driving a half bridge, as illustrated in the accompanying drawings, of which:

- Figure 1 illustrates the circuit representation of a half bridge;

- Figure 2 illustrates the circuit representation of an H-bridge;

- Figure 3 illustrates the circuit representation of a three-phase bridge;

- Figure 4 illustrates the circuit representation of a "boost" converter;

- Figure 5 illustrates the circuit representation of a "buck" converter;

- Figure 6 schematically illustrates a driving circuit of a transistor of the half bridge of Figure 1 , according to the present invention;

- Figure 7 schematically illustrates a driving circuit for two transistors of a half bridge, according to the present invention;

- Figure 8 illustrates an LDO converter used to generate the second supply voltage V2 of Figure 6;

- Figure 9 illustrates the waveforms of signals of the driving circuit of Figure 6;

- Figure 10 schematically illustrates the driving circuits of the transistors of the half bridge of Figure 1 ;

- Figure 11 illustrates the periodic trend of the command signals of the driving circuits of Figure 10, according to the present invention;

- Figure 12 illustrates the waveform of a voltage with a switch-on pulse employed in the driving circuit of Figure 6.

Detailed description of preferred embodiments of the invention

Number 1 indicates a half bridge comprising at least two devices 2, 3 arranged one above the other.

One of the two devices 2, connected to ground, is often referred to as "lower", while the other device 3 is referred to as "upper".

In accordance with an aspect of the invention, one of the devices - herein indicated as "first device" and number 2 - is a transistor or a diode.

The other device - herein indicated as the "second device" and number 3 - is a transistor.

As is known, the half bridge represents a basic electronic module that can be used in an H-bridge, which is formed by two half bridges adapted to drive a load L, for example an inductance (see figure 2) or any other load. Each half bridge represents a branch or a leg of the H-bridge.

By way of example, the half bridge circuit 1 can also be used in a three- phase bridge (see figure 3) or to drive a "boost" converter (see figure 4) or a "buck" converter (see figure 5).

The driving of the two devices 2, 3 of the half bridge 1 takes place by means of signals which respond to a periodic modulation pattern configured in such a manner that in a period T the first device 2 assumes a switched on configuration for a fraction of period toN.

The ratio between the fraction of period toN in which the device is switched on and the period T itself is known as "duty cycle", hereinafter referred to as d and expressed by the formula: d = toN / T.

It is known that the devices of a half bridge cannot conduct simultaneously, that is, they cannot be both in the switched on configuration. Should this happen, there would be the so-called "shoot- through" which, with the circulation of a high current between power supply and ground, could destroy the devices.

In order to avoid this problem, it is made sure to switch off the device that is on before switching on the other one (the one that is off). This means that there will be a transient of limited duration in which both devices will be off.

The method proposed herein provides for forcing the second device 3 (which is the transistor) in a current generator configuration controlled by a switch-on pulse PulsecsT for an interval of time tst that is greater than a time constant T of the second device 3. At the same time, the first device 2 (which is a transistor or a diode) is instead maintained in the switched on configuration for the whole fraction of period toN = d * T.

In this way, a controlled short-circuit condition is obtained, imposed by the switch-on PulsecsT whose duration tst and whose amplitude can be adjusted to keep under control the average power P _avg dissipated over the period T by the second device 3. The step of adjusting the duration of the interval of time tst is based on the calculation or prediction of the average power P _avg dissipated over the period T.

The lower limit of the duration tst is dictated by the time constant T of the second device 3, which is the reciprocal of the shear pulsation that characterizes it.

Preferably, the interval of time tst during which the second device 3 is forced in the controlled current generator configuration is greater than four times the time constant T of the transistor.

Advantageously, in addition to adjusting the interval of time tst, the width of the switch-on pulse PulsecsT, is adjusted, as will be better explained below.

By indicating with VDC the voltage of the DC power source and 1st the current circulating in the second device 3 during the controlled shoot- through event, the average power dissipated over the period Pavg by the second device 3 is calculated as:

Pavg = VDC 1st tst/T.

In this formula there are two quantities which in the proposed method are variables:

- the duration of the controlled short-circuit condition, i.e. tst;

- the current circulating in the second device 3, i.e. 1st.

Having two degrees of freedom allows to further increase the granular control over the power dissipated by the second device.

In fact, the adjustment of the duration (i.e. tst) has a lower limit dictated by the time constant T of the second device 3. This limit can be compensated by varying the current 1st. In this way, the average power interval Pavg that can be dissipated by the second device 3 is extended.

Furthermore, the adjustment of the duration also has an upper limit, linked to the maximum normal duty-cycle to be guaranteed.

In accordance with an aspect of the invention, the proposed method further comprises a step of measuring a circulating current value in the second device 3 when it is in the controlled current generator configuration.

From the current value thus measured, a corresponding temperature value is obtained for the second device 3.

In order to obtain the temperature from the shoot-through current it is first of all necessary to carry out a thermal characterization of the second device 3 so as to establish a relation between the current circulating in the second device 3 and the temperature.

In accordance with an aspect of the invention, the thermal characterization is performed by means of the calibration technique described in the scientific article by A. Soldati, R. Menozzi, C. Concari, "In-Circuit Shoot- through-Based Characterization of SiC MOSFET TSEP Curves for Junction Temperature Estimation", ECCE 2020, October 2020.

However, other calibration techniques can also be used.

In this way, the shoot-through current is used as the TSEP variable for the indirect measurement of the temperature of the second device 3.

In accordance with an aspect of the invention, the measurement of the current is made by sampling the shoot-through current preferably around the centre of the switch-on pulse PulsecsT, as can be seen in figure 12.

In fact, although the switch-on pulse PulsecsT is represented ideally as rectangular, it features an exponential transient of the 1 st order or 2nd order (if parasites are present), so that, being placed in the middle of the pulse duration, sampling is certain after the rising transient has been already ended.

By sampling the current value in the middle of the switch-on pulse PulsecsT and by searching for its value on the TSEP characteristic curve previously constructed, the corresponding temperature value is obtained. Various interpolation algorithms of known type can be used to find the current on the TSEP characteristic curve, such as observers, Kalman filters, etc.

In accordance with an aspect of the invention, the measurement of the current is made by means of several samplings during the switch-on pulse PulsecsT, both in real time and in equivalent time.

Number 10 indicates a circuit for driving the second device 3.

In accordance with an embodiment, illustrated in figure 6, the driving circuit 10 comprises:

- a first three-state logic gate 11 having an input In configured to receive an input signal Si, a further input En configured to receive a first enabling signal SEH and an output Un ;

- a second three-state logic gate 12 having an input I12 configured to receive an input signal Si, a further input E12 configured to receive a first enabling signal SE12 and an output U12.

The first three-state logic gate 1 1 is supplied by a first fixed supply voltage V1 , while the second three-state logic gate 12 is supplied by a second supply voltage V2 that is variable as a function of a control signal VST.

The inputs In, I12 of the two three-state logic gates 1 1 , 12 are configured to receive the same input signal Si.

The first enabling signal SEH and the second enabling signal SE12 are complementary in such a manner that at each period T only one of the two three-state logic gates 1 1 , 12 is in a high impedance condition.

To obtain complementary signals it is possible to generate only one of them, for example the first enabling signal SEH , and to obtain the complementary thereof by means of an inverter gate (not illustrated).

As is known, the output of a three-state logic gate, in addition to the two logic levels present in binary logic ("0" - "1" or "low" - "high"), can also assume a high impedance state. The state of the three-state logic gate is determined by the relative enabling signal.

For example, the two three-state logic gates 1 1 , 12 are preferably three- state buffers so that in the high impedance state they behave like open switches.

By indicating with I the input, with E the enabling signal and with U the output of a three-state buffer, the truth table is as follows:

It is therefore understood that, when the enabling signal E = "0" (or low), the output U of the three-state logic gate moves to high impedance regardless of the value present on the input I, therefore the gate is comparable to an open switch.

When the enabling signal E = "1" (or high), the output U assumes a value equal to the input I, therefore the gate is comparable to a closed switch.

The three-state logic gates 11 , 12 can have unity gain or perform the function of amplification.

As regards the adjustment of the duration tst of the switch-on pulse, this can take place for example through:

- prediction of the average power P _avg dissipated over the period T by the second device 3 starting from a mathematical modelling of the latter (according to known predictive methods);

- starting from the above formula, i.e.:

Pavg = VDC 1st tst/T.

As regards the adjustment of the amplitude of the switch-on pulse PulsecsT, in accordance with one embodiment the driving circuit 10 comprises an LDO converter (acronym for "Low-DropOut"), indicated with number 20.

The LDO converter 20, in response to the control signal VST is configured to reduce the amplitude of the first supply voltage V1 and to provide as output the second supply voltage V2.

An implementation pattern of the LDO converter 20 is illustrated in figure 8, in which it can be recognized: - an optocoupler 21 controlled by the modulated control signal VST (e.g. PWM);

- a low-pass filter 22 downstream of the optocoupler 21 ;

- an operational amplifier 23 downstream of the low-pass filter 22;

- a push-pull output stage 24.

In accordance with another embodiment, instead of the LDO converter, a switching (e.g. buck) converter or a switched capacitance converter is used.

In accordance with an aspect of the invention, the control signal VST is a digital or analogue modulated signal.

For example, the control signal VST is a PWM signal or a pulse density modulated signal.

Beyond the various forms that the modulated control signal VST can assume, the second supply voltage V2 depends thereon by means of a monotonic function.

Preferably, the driving circuit 10 also comprises:

- at least one resistor 14 located downstream of the first three-state logic gate 11 , i.e. configured to receive the signal coming from the output Ui 1 of the first three-state logic gate 11 ;

- a further resistor 15 located downstream of the first three-state logic gate 12, i.e. configured to receive the signal coming from the output U12 of the second three-state logic gate 12.

By way of example, figure 11 illustrates the time trend over a period T of the command signals of the driving circuits 10_2, 10_3 of two devices 2,3 of the half bridge 1 (fig. 10). In this case, therefore, both devices 2, 3 are transistors.

With reference to the first driving circuit 10_2, the following are represented:

- a first input signal Si_2 configured to supply the input In of the first three-state logic gate 11 and the input I12 of the second three-state logic gate 12 of the first driving circuit 10_2; - a first enabling signal SEH configured to supply the further input E11 of the first three-state logic gate 11 of the first driving circuit 10_2;

- a second enabling signal SEI2, complementary to the first enabling signal SEH and configured to supply the further input E12 of the second three-state logic gate 12 of the first driving circuit 10_2.

With reference to the second driving circuit 10_3, the following are represented:

- a second input signal Si_3 configured to supply the input In of the first three-state logic gate 11 and the input I12 of the second three-state logic gate 12 of the second driving circuit 10_3;

- a third enabling signal SEIT configured to supply the further input E11 of the first three-state logic gate 11 of the second driving circuit 10_3;

- a fourth enabling signal SEI2’, complementary to the third enabling signal SE-IT and configured to supply the further input E12 of the second three-state logic gate 12 of the second driving circuit 10_3.

To have the driving according to the method proposed herein, the two input signals Si_2, Si_3 at each period T must satisfy a well-defined relation.

In particular, at each period T one of the input signals will assume a high digital level for a fraction of period toN in such a way as to allow the corresponding transistor to be switched on and the other input signal will assume a high digital level only for the time interval tst greater than the time constant T SO as to force the corresponding transistor (initially off) in a controlled current generator configuration.

Figure 7 instead illustrates a more generic diagram of the devices 2, 3 of the half bridge 1 , with respective control circuits 10 which receive four signals as input: CMD, CST, EN and the control signal VST.

These signals are illustrated in Figure 9, where it can be seen that:

- the signal CMD is the normal switch-on signal of the device 2, 3, which determines the duty-cycle thereof;

- the signal CST is the one that carries the information about the duration of the switch-on pulse Pulsecsi;

- the signal EN is the enabling signal which enables only one of the two three-state logic gates 11 , 12 so that there is no conflict;

- the control signal VST the signal used to obtain the second supply voltage V2.

With the aim of making a parallel with the signals used in figure 6, the following applies:

- the input signal S1 of the two three-state logic gates 11 , 12 is given by the "OR" of the signals CMD and CST.

- The signal EN is the enabling signal from which the two complementary signals SEH , SEi2 are obtained: one coincides with the enabling one and the other one with the negated value thereof.

The half bridge 1 of figure 7 also comprises two clampers indicated with CL2, CL3. Each clamper is connected between the output terminal (drain or collector) of the corresponding device and the reference terminal (source or emitter).

The task of the clamper is to limit the voltages VON, 2 and VON, 3 to a certain level VON, max greater than the maximum voltage of the switched on device that can be had in practical conditions.

In power applications, the controlled current generator configuration is undesirable for a transistor as it is linked to a high power dissipation which can lower the efficiency of the circuit or alter the performance thereof. Furthermore, if the transistors were in this configuration for a long time, they could be damaged due to the high temperatures reached.

In this context, the definitions of "switched on configuration" and "controlled current generator configuration" must be correlated to the type of transistors used.

Since the nomenclature used in the reference texts can often give rise to ambiguity and sometimes contradictions, it is preferred in this context to provide an ad hoc nomenclature, set out below.

In the embodiments described and illustrated herein, the second device 3 of the half bridge 1 is a MOSFET transistor (acronym of the expression "Metal-Oxide-Semiconductor Field-Effect Transistor").

As is known, a MOSFET transistor has three terminals - Gate, Source, Drain - to which reference will be made in the following.

The MOSFET can be used as a linear amplifier or as a switch. In this context, the focus is solely on the use of the MOSFET as a switch. More often it is spoken of operation as a "switch" or "switching".

Briefly, the operation of the MOSFET as a switch is as follows:

- If the voltage between Gate and Source VGS is lower than a threshold voltage Vth, the current entering the Drain ID and the one exiting the Source Is are null. The MOSFET is therefore located in the interdiction region (i.e. it is off) and is comparable to an open switch.

- If the voltage between Gate and Source VGS is greater than the threshold voltage Vth, there is a current entering from the Drain ID and exiting the Source. The voltage between Drain and Source VDS is very low, approximating 0 Volt. The MOSFET is therefore located in the triode region and its behaviour approximates that of a closed switch. In this context, the "switched on configuration" of the MOSFET means the configuration whereby the MOSFET is in the triode region.

In the operation as a switch, the MOSFET is temporarily in the saturation region during the interdiction-to-triode switching transient, and vice versa.

In the saturation region, the voltage between Gate and Source VGS is greater than the threshold voltage Vth while the voltage between Gate and Drain VGD is lower than the threshold voltage Vth. In this case, the Drain ID current can be determined according to the following formula:

ID = K (VGS-Vth) ² where K is the conductance and depends on manufacturing technology parameters, geometric dimensions and temperature.

The threshold voltage Vth also depends on the temperature.

Hence, in this context, "controlled current generator configuration" means the configuration whereby the MOSFET is in the saturation region and behaves like a voltage controlled current generator.

In the case of MOSFET, the two three-state gates 11 , 12 of the driving circuit 10 are drivers connected between the gate and the source.

In this case, it is the voltage between the Gate and the VGS that exhibits a switch-on pulse PulsecsT having an amplitude and an adjustable duration, as can be seen in figure 9. In particular, by using the modulated control signal VST the amplitude of the first supply voltage V1 is reduced and thus the second supply voltage V2 for the second three-state logic gate 12 is obtained. The output U12 of this gate is the gate voltage.

In fact, by varying VGS the current circulating in the second device 3 varies. Therefore, if the second device 3 is a MOSFET transistor, the method provides that it is forced over a period T to work in the saturation region while the first device 2 works in a triode region for the fraction of period toN = d * T.

The amplitude of the VGS pulse can assume any value comprised between the threshold voltage of the device and the Miller voltage of the same, i.e. the voltage that marks the passage between the operating region from "switch on configuration" to that of "controlled current generator configuration".

The measurement of the Drain ID current is made by means of a current sensor placed on the Drain or on the Source.

With reference to figure 7, the current measurement of the first device 2 can be made at the points indicated with A2, B2 and the current measurement of the second device 3 can be made at the points indicated with A3, B3.

Point A3 can also be on the terminal VH and point B2 on the terminal VL. If the half bridge is part of a more complex circuit (e.g. full bridge or three- phase bridge), however, it is necessary to pay attention to the fact that detecting the current on the terminal VH means detecting the sum of the currents of all the half bridges.

In accordance with an aspect of the invention, the first device 2 is also a transistor, so that it can also be forced to assume a controlled current generator configuration, according to a pattern similar to that described for the second transistor 3.

In this case, it is possible to measure the simultaneous temperature of both devices 2, 3 relying on two different TSEP variables: the shoot- through current and the voltage of the switched on device with variable current or fixed current.

The circuit illustrated in figure 7 can therefore be adapted to make TSEP measurements of a different type: for example for one device through the shoot-through current, and for the other device through the voltage of the switched on device.

In accordance with an alternative embodiment (not illustrated), the second device 3 of the half bridge 1 is a BJT transistor (acronym of the expression "Bipolar Junction Transistor").

As is known, a BJT transistor has three terminals - Base, Emitter, Collector

- to which reference will be made in the following.

Briefly, the operation of the BJT as a switch is as follows:

- If the current entering the Base IB is null, also the current entering the Collector lc and the one exiting the Emitter IE are null. The BaseEmitter and Base-Collector junctions are both reverse biased. The BJT is therefore located in the interdiction region (i.e. it is off) and is comparable to an open switch.

- If the current entering the Base IB is sufficiently high, there is a current lc entering from the Collector and exiting the Emitter. The Base-Emitter and Base-Collector junctions are both forward biased. The voltage between Collector and Emitter VCE is very low, approximating 0 Volt. The BJT is therefore located in the saturation region and its behaviour approximates that of a closed switch. In this context, the "switched on configuration" of the BJT means the configuration whereby the BJT is in the saturation region.

In the operation as a switch, the BJT is temporarily in the forward-active region during the interdiction-to-saturation switching transient, and vice versa.

In the forward-active region the Base-Emitter junction is forward biased and the Collector-Base junction is reverse biased.

The current of Collector l _c is proportional to the current of Base IB according to the formula: lc = p IB where p is the current gain.

Hence, in this context, "controlled current generator configuration" means the configuration whereby the BJT is in the forward-active region and behaves like a voltage controlled current generator.

Therefore, if the second device 3 is a BJT transistor, the method provides that it is forced over a period T to work in the forward-active region while the first device 2 works in a saturation region for the fraction of period toN = d * T.

The measurement of the Collector l _c current is made by means of a current sensor placed on the Collector or on the Emitter.

In the case of BJT, the two three-state gates 1 1 , 12 of the driving circuit 10 are drivers connected between the base and the collector.

In accordance with an alternative embodiment (not illustrated), the second device 3 of the half bridge 1 is an IGBT transistor.

As is known, an IGBT transistor has three terminals - Gate, Collector and Emitter - to which reference will be made in the following.

Briefly, the operation of the IGBT as a switch is as follows:

- If the voltage between Gate and Emitter VGE is lower than a threshold voltage Vth, the current entering the collector lc and the one exiting the Emitter IE are null. The IGBT is therefore located in the interdiction region (i.e. it is off) and is comparable to an open switch.

- If the voltage between Gate and Emitter VGE is greater than the threshold voltage Vth by an amount such that the voltage between the Collector and the Emitter VCE is about 0 Volt, there is a current entering the collector lc and exiting the Emitter. The IGBT is therefore located in the saturation region and its behaviour approximates that of a closed switch. In this context, the "switched on configuration" of the IGBT means the configuration whereby the IGBT is in the saturation region.

During the interdiction-to-saturation switching transient and vice versa, the IGBT temporarily is in a linear region in which the collector lc current is in first approximation proportional to the so-called overdrive voltage (VoE-Vth) according to the formula: lc = gf (VGE-Vth) where gt is the transconductance.

Hence, in this context, "controlled current generator configuration" means the configuration whereby the IGBT is in a linear region and behaves like a voltage controlled current generator.

The measurement of the Collector l _c current is made by means of a current sensor placed on the Collector or on the Emitter.

In the case of IGBT, the two three-state gates 11 , 12 of the driving circuit 10 are drivers connected between the gate and the collector.

From the description provided, the features of the method and of the circuit for driving a half bridge according to the present invention are clear, as are the advantages.

In particular, thanks to the fact that a transistor is forced in the controlled current generator configuration for an adjustable interval of time and by means of a pulse of adjustable amplitude, the method allows carrying out a control of the average power dissipated over the period by the transistor even when it is crossed by low current levels.

Furthermore, the proposed method makes it possible to use the shoot- through current as a TSEP variable to make indirect measurements of temperature of the transistor. Therefore, it is sufficient to exploit the current sensors that are normally already present in the power circuits, as long as they have sufficient bandwidth to detect the current pulse during the shoot- through event. The proposed solution is therefore structurally simple as it does not require additional measurement or clamping components besides the current sensors already present.

Furthermore, obtaining the characteristic curve of the shoot-through current as TSEP does not require a circuit calibration in a controlled temperature environment.

Furthermore, by varying the amplitude of the switch-on pulse, the proposed measurement method is dynamically adaptable to devices from different batches, therefore with different threshold voltages.

Again for the same reason, it is also possible to adapt the measurement to the aging of the devices.

Furthermore, the proposed method allows making the measurement even on a single device, unlike known solutions in which the current TSEP variables usually require several devices.

Furthermore, by varying the amplitude of the switch-on pulse it is possible to adapt the measurement so as to have a shoot-through current high enough to guarantee a better signal-to-noise ratio than the technique based on the measurement of the saturation current of D. Bergogne, B. Allard and H. Morel.

Furthermore, the double degree of freedom facilitates current measurement even for circuits with limited bandwidth.