Title:
A METHOD AND A CIRCUIT FOR RETIMING A DIGITAL DATA SIGNAL
Document Type and Number:
WIPO Patent Application WO2000031915
Kind Code:
A3
Abstract:
By application of a method and a circuit for retiming a digital data signal (Din) consisting of a number of successive bits, wherein the data signal is sampled by an internal clock signal (Ckint) generated from an external clock signal (Ckref), the internal clock signal (Ckint) is phase locked to the data signal (Din) so that the latter is sampled approximately in the centre of every bit. By generating the internal clock signal from the external clock signal, and at the same time phase locking it to the dta signal, the internal clock signal will automatically adjust itself so that the data signal is sampled at the appropriate point in time, i.e. in the centre of the bit period. As a result, there are no strict requirements as to the synchronisation between the data signal and the clock signal, and an individual adjustment of the synchronisation in preceding circuits is thus avoided.
Inventors:
CHRISTENSEN STEEN BAK (DK)
Application Number:
PCT/DK1999/000647
Publication Date:
October 05, 2000
Filing Date:
November 23, 1999
Export Citation:
Assignee:
GIGA A S (DK)
CHRISTENSEN STEEN BAK (DK)
CHRISTENSEN STEEN BAK (DK)
International Classes:
H03L7/081; H03L7/087; H03L7/14; H03L7/089; H04L7/00; (IPC1-7): H04L7/02
Foreign References:
| GB2233177A | 1991-01-02 | |||
| EP0663744A1 | 1995-07-19 | |||
| US4339823A | 1982-07-13 | |||
| US4707842A | 1987-11-17 | |||
| US5539344A | 1996-07-23 | |||
| DE3012075A1 | 1981-10-08 |
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