TECHNICAL FIELD

Embodiments herein relate to signal processing circuits, such as a signal cancellation circuit for a power amplifier. In particular, a controllable delay unit configured to manage amplitude slope of an input signal and phase slope of the input signal over a frequency range as well as a method for managing an amplitude slope of the input signal and a phase slope of the input signal over a frequency range are disclosed. A program code, corresponding to the controllable delay unit, is also disclosed.

BACKGROUND

Within telecommunications systems, signals are often amplified using for example a power amplifier. In scenarios, where the signals fed to the power amplifier vary within a relatively wide bandwidth, distortion of the amplified signal may occur. In order to compensate for the distortion, a feed-forward system, including the power amplifier, may be employed. The feed-forward system utilizes signal cancellation, which means that a distortion, or error, extracted from an output of the power amplifier is added in opposite phase at the output of the feed-forward system in order to cancel the distortion. The distortions occur due to non-linear behavior of the power amplifier. The feed-forward system may be implemented using discrete or integrated circuits. For example, it has become more and more common to use Application Specific Integrated Circuits (ASICs) when designing and implementing this kind of system. A reason for this may be that ASICs may in large quantities become very cost effective.

A known feed-forward system 100 comprises a set of components as shown in Figure 1 . The set of components include a power amplifier 101 , an error extractor 102, a vector modulator 103, an isolator 104, a delay filter 105 and an adder 106. The power amplifier 101 is configured to receive an input signal 106 for which it is desired to at least reduce distortion of the above mentioned kind. Thus, the feed-forwards system 100 outputs, from the adder 106, an output signal 107 for which distortion is reduced. The output signal 107 originates for a combination of an error signal, passing through the error extractor 102 and the vector modulator 103, and a main signal, passing through the isolator 104 and the delay filter 105. For this purpose, the power amplifier 101 is operatively connected to the error extractor 102, which also is configured to receive the input signal 106. The error extractor 102 is operatively connected to the vector modulator 103. The power amplifier 101 is also operatively connected to the delay filter 105 via the intermediate isolator 104, which provides coarse delay matching of the error and main signals. At the adder 106, the signals are added in opposite phase in order to cancel the distortion in the main signal.

Due to imperfections in the feed-forward system 100, such as in the isolator 104 and the delay filter 105, a manual procedure of tuning of delay and gain slope is required in order to achieve cancellation over the desired bandwidth. The

imperfections may occur due to manufacturing variations among the components of the system, temperature drift and the like. The manual procedure may

disadvantageously include manual swapping of one or more of the components of the feed-forward system 100. A further disadvantage is that the procedure may be costly and time consuming.

SUMMARY

An object is to provide an integrated circuit, such as an ASIC block, that alleviates or at least reduces the above mentioned disadvantages.

According to an aspect, the object is achieved by a controllable delay unit configured to manage amplitude slope of an input signal and phase slope of the input signal over a frequency range. The controllable delay unit comprises an input port configured to receive the input signal, and a delay chain configured to provide discrete phase slopes of the input signal over the frequency range at a first set of switchable ports and at a second set of switchable ports, wherein the delay chain comprises at least two delay elements, providing the discrete phase slopes of the input signal, and at least one of the first set of switchable ports provides a first discretely delayed signal and at least one of the second set of switchable ports provides a second discretely delayed signal. Moreover, the first set of switchable ports is configured to extract the first discretely delayed signal, derived from the input signal, with a first phase slope over the frequency range. Additionally, the second set of switchable ports is configured to extract the second discretely delayed signal, derived from the input signal, with a second phase slope over the frequency range. Furthermore, the controllable delay unit comprises a combining sub-unit configured to combine the first and second discretely delayed signals into an output signal, wherein the amplitude slope of the output signal is dependable on a difference between phase slope of the first discretely delayed signal and the second discretely delayed signal and the phase slope of the output signal is dependable on combined phase slope of the first and second discretely delayed signals, and an output port configured provide the output signal from the combining sub-unit.

The controllable delay unit further comprises a controlling unit configured to control, based on a control signal for setting the amplitude slope and phase slope of the output signal, the first and second set of switchable ports of the delay chain, wherein the control signal is adapted to cause at least one of the switchable ports of the first set to be switched on and at least one of the switchable ports of the second set to be switched on. According to another aspect, the object is achieved by a method, performed by a controllable delay unit, for managing an amplitude slope of an input signal and a phase slope of the input signal over a frequency range. The controllable delay unit receives the input signal and discretely delays the input signal to provide a first discretely delayed signal and a second discretely delayed signal. Next, the controllable delay unit combines the first and second discretely delayed signals into an output signal, wherein a gain slope of the output signal is dependable on a difference between delay of the first discretely delayed signal and the second discretely delayed signal and the phase slope of the output signal is dependable on combined delay of the first and second discretely delayed signals. The controllable delay unit also controls, based on a control signal for setting the gain slope and phase slope of the output signal, a first and a second set of switchable output ports of a delay chain for providing the discretely delayed first and second signals, wherein at least one of the switchable output ports of the first set is switched on and at least one of the switchable output ports of the second set is switched on. The output signal is sent by the controllable delay unit to an output port.

According to further aspects, the object is achieved by a radio node and a feed-forward system, comprising the controllable delay unit as above In some embodiments of the method, a user is allowed to set desired amplitude slope, e.g. gain slope, by combining two different, arbitrary and

independent signals from the delay chain, e.g. a discrete step time delay chain. An optional addition of a variable gain amplifier (VGA) in one, or both, of the signals after the delay chain may enable fine tuning of amplitude slope. If a VGA capable of changing sign of the signal received at it, the amplitude slope may be increase as well as decrease. E.g. a multiplicator type VGA may be used. Desired phase slope is then set by shifting position, i.e. discrete delay steps, of the two signals output from the delay chain an equal amount of delay steps, either forward or backwards.

Forwards may be that the phase slope is increased and backwards may be that the phase slope is decreased. In this manner, desired amplitude slope and phase slope of the input signal is obtained.

In this context, it deserves to be mentioned that the term "phase slope" as used herein may refer to a group delay, or a constant group delay, over the frequency range of the controllable delay unit. The group delay is the derivative of the phase with respect to frequency. Therefore, a linearly increasing phase gives a constant group delay.

Using embodiments of the controllable delay unit in conjunction with a feedforward system, comprising a vector modulator, provides control of amplitude and phase as well as amplitude slope and phase slope over a large bandwidth.

Implementation preferably allows the control signal to be managed, e.g. to be set, over a digital interface using software. The software may be a user interface, such as a graphical user interface, or an automatic tuning program including a suitable algorithm.

An advantage is that the amplitude and phase slope of the output signal may be conveniently controlled by means of the control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

Figure 1 is a block diagram illustrating a feed-forward system according to prior art,

Figure 2 is an illustration signal combination according to known principles, Figure 3 is a block diagram illustrating an exemplifying controllable delay unit according to embodiments herein, Figure 4 is another block diagram illustrating an exemplifying controllable delay unit according to embodiments herein,

Figure 5 is a further block diagram illustrating an exemplifying controllable delay unit according to embodiments herein,

Figure 6 is yet another block diagram illustrating a feed-forward system comprising the controllable delay unit according to embodiments herein,

Figure 7 is a flowchart illustrating embodiments of the method in the radio network node, and

Figure 8 is a block diagram illustrating an exemplifying delay element.

DETAILED DESCRIPTION

Throughout the following description similar reference numerals have been used to denote similar elements, units, modules, blocks, actions, steps, components, circuits, nodes, parts, items or features, when applicable. In the Figures, features that appear in some embodiments are indicated by dashed lines.

In order to better appreciate the operation of the controllable delay unit as described below with reference to Figure 3, a brief description of signal combination according to known principles is provided.

Thus, Figure 2 is an illustration of amplitude and phase variation for a signal passing through two delay elements ΤΊ, T ₂ in a respective branch of a circuit 200 according to known manners. In this example, an input signal IN is feed into the circuit 200 including the respective delay elements T _{1 5} T ₂ . After the input signal IN has passed the respective delay elements T T ₂ two differently delayed signals are obtained. A first signal S1 , passing through delay element J , has a certain amplitude and phase variation over frequency that is different from a second signal S2, passing through delay element T ₂ .

After the first and second signals have been combined, in a combining component 201 , a resulting signal is obtained. An out-amplitude and an out-phase for the resulting signal are illustrated in the diagrams to the right of the circuit 200. A notch N illustrates where the phase difference between the first and second signals is 180°. From the Figure, it can be seen that for a selected frequency range below the notch, a negative amplitude slope is obtained. Similarly, a positive amplitude slope is obtained for a frequency range selected above the notch. Now an exemplifying controllable delay unit 300 according to embodiments herein is described with reference to Figure 3. In some examples, the controllable delay unit 300 may comprise, or be embodied in the form of, an Application Specific Integrated Circuit (ASIC) block, e.g. realized from a VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) code in case of a digital ASIC implementation. The controllable delay unit may thus be referred to as the ASIC block. In case of an analogue ASIC implementation, the ASIC block may be realized from e.g. Radio Frequency Complementary Metal-Oxide Semiconductor (RF-CMOS), RF-Bipolar CMOS (RF-BiCMOS) and the like. The controllable delay unit 300 is configured to manage amplitude slope of an input signal 310 and phase slope of the input signal 310 over a frequency range.

The controllable delay unit 300 comprises an input port 301 configured to receive the input signal 310.

The controllable delay unit 300 also comprises a delay chain 303 configured to provide discrete phase slopes of the input signal 310 over the frequency range at a first set 306 of switchable ports and at a second set 307 of switchable ports. In this example, the delay chain 303 may thus be embodied in the form of a delay chain sub-block, or delay chain sub-unit. As a possibility, it may be noted that further sets of switchable ports may be used to provide further possible combinations of ports that are active and/or in-active. However, the same or similar result as with two sets of switchable ports may be obtained.

The delay chain 303 comprises at least two delay elements 304, 305, providing the discrete phase slopes of the input signal, and at least one of the first set 306 of switchable ports provides a first discretely delayed signal S1 and at least one of the second set 307 of switchable ports provides a second discretely delayed signal S2. The at least two delay elements 304, 305 may be delay sub-units, or sub- blocks, of the controllable delay unit 300. Exemplifying delay elements are shown with reference to Figure 8.

The first set 306 of switchable ports are configured to extract the first discretely delayed signal S1 , derived from the input signal 310, with a first phase slope over the frequency range. The first phase slope is thus one of the discrete phase slopes provided by the at least two delay elements 304, 305. An example of the extraction of the first discretely delayed signal S1 is shown in Figure 4 and/or 5 below. The second set 307 of switchable ports are configured to extract the second discretely delayed signal S2, derived from the input signal 310, with a second phase slope over the frequency range. The second phase slope is different from the first phase slope. The second phase slope is thus another of the discrete phase slopes provided by the at least two delay elements 304, 305. An example of the extraction of the second discretely delayed signal S2 is shown in Figure 4 and/or 5 below.

The controllable delay unit 300 further comprises a combining sub-unit 308 configured to combine the first and second discretely delayed signals into an output signal 311 . The combining sub-unit 308 may be a sub-block of the ASIC block forming the controllable delay unit 300. The amplitude slope of the output signal 31 1 is dependable on a difference between phase slope of the first discretely delayed signal and the second discretely delayed signal and the phase slope of the output signal 31 1 is dependable on combined phase slope of the first and second discretely delayed signals.

The combining sub-unit 308 performs a summation of the first and second discretely, and differently, delayed versions of the input signal. Thereby, the amplitude slope is generated. A delay is essentially the same as a linear slope in phase over frequency and summing the two signals at the phase extreme of 180 degrees ideally cancels the output signal. The output amplitude has a sinusoidal relationship to the phase difference between the two input signals but usually the bandwidth requirement in applications like feed-forward, even in future mobile systems with extreme bandwidth, does not suffer much from this deviation from ideal behaviour. Since the sinusoidal relationship is approximated with a linear slope, a first order compensation is provided.

In this manner, the combination of the first and second set 306, 307 of switchable ports together with the delay elements 304, 305 allows for arbitrary, and differently delayed, signals to be combined generating an amplitude slope on the output signal. For a practical approach only two switchable ports are active, one selected from the first set of switchable ports and one selected from the second set of switchable ports.

Furthermore, the controllable delay unit 300 comprises an output port 302 configured to provide the output signal 31 1 from the combining sub-unit 308.

Moreover, the controllable delay unit 300 comprises a controlling unit 309 configured to control, based on a control signal 312 for setting the amplitude slope and phase slope of the output signal 31 1 , the first and second set of switchable ports of the delay chain 303. The control signal 312 is adapted to cause at least one of the switchable ports of the first set 306 to be switched on and at least one of the switchable ports of the second set 307 to be switched on. As an example, each of the first and second set 306, 307 of switchable ports comprises three ports. Then, the control signal may be configured as "100 001" in order to switch on the first port of the first set and the last port of the second set.

In more detail, in order to generate a desired amplitude slope, the distinctive 180 degree notch N in Figure 2 is placed, by switching in appropriate difference in delays, well outside the frequency band of operation, either above or below said frequency band of operation. The delays of the first and second signals are caused by one or more of the at least two delay elements. The amplitude slope will then depend on the difference in delay between the signals selected and is fine-tuned with the VGA.

Placing the notch below instead of above the frequency range of interest inverts the sign of the amplitude slope, as subtracting one of the delayed signals from the other instead of summing them also does. The subtraction feature is easily implemented by e.g. using a Gilbert multiplicator type of VGA.

The controllable delay unit 300 may comprise a Variable Gain Amplifier (VGA) 313, operatively connected to the combining sub-unit 308, for tuning of gain of the first and/or second discretely delay signals. In this manner, amplitude slope of the output signal 31 1 may be adjusted more accurately than without VGA.

The controllable delay unit 300 may comprise a processing sub-unit 320, such as a processing sub-block, processing core, processor core or the like.

Additionally, the controllable delay unit 300 may comprise a memory 330, such as a memory sub-unit, a memory sub-block or the like. The memory may be used to store information about which ports among the first and second sets of ports to be switched on or off.

Thanks to the controlling sub-unit 309 in combination with the delay chain 303 the need for discrete component tuning or swapping, as mentioned in the

background section, is alleviated. Implementing the delay chain together with the required switchable ports and VGAs in an ASIC, preferably together with a vector modulator and a serial digital interface, provides a one-chip fully programmable solution removing the need for discrete component tuning or swapping.

In another example, a radio node 340 is proved. The radio node 340 comprises the controllable delay unit 300 according to the embodiments above. In particular, the radio node 340 may comprise any feed-forward system, such as the feed-forward system 600 described above.

The radio node 340 may be a radio network node, such as a radio base station, an eNode B, a Node B, a base station controller, a base station system or the like, or a user equipment.

As used herein, the term "radio network node" may refer to is a piece of equipment that facilitates wireless communication between user equipment (UE) and a network. Accordingly, the term "radio network node" may refer to a Base Station (BS), a Base Transceiver Station (BTS), a Radio Base Station (RBS), a NodeB in so called Third Generation (3G) networks, evolved Node B, eNodeB or eNB in Long Term Evolution (LTE) networks, or the like. In UMTS Terrestrial Radio Access Network (UTRAN) networks, where UTMS is short for Universal Mobile

Telecommunications System, the term "radio network node" may also refer to a Radio Network Controller. Furthermore, in Global System for Mobile Communications (GSM) EDGE Radio Access Network (GERAN), where EDGE is short for Enhanced Data rates for GSM Evolution, the term "radio network node" may also refer to a Base Station Controller (BSC).

As used herein, the term "user equipment" may refer to a mobile phone, a cellular phone, a Personal Digital Assistant (PDA) equipped with radio

communication capabilities, a smartphone, a laptop or personal computer (PC) equipped with an internal or external mobile broadband modem, a tablet PC with radio communication capabilities, a portable electronic radio communication device, a sensor device equipped with radio communication capabilities or the like. The sensor may be any kind of weather sensor, such as wind, temperature, air pressure, humidity etc. As further examples, the sensor may be a light sensor, an electronic switch, a microphone, a loudspeaker, a camera sensor etc. Figure 4 is an example of the controllable delay unit according to

embodiments herein. As mentioned above, the same reference numerals have been used to denote the same or similar feature(s).

In this example, the first set of switchable ports 306 is realized in the form of a first group A of switches. The switches may be solid state transistor switches. The second set of switchable ports 307 may be realized in the form of a second group B of switches.

In the example implementation of Figure 4, the switches are arranged such as to extract the first and second signals, from a set of delay elements T, to be combined in a summation sub-unit 308. In other examples, such as indicated by Figure 3, the switches, shown as switchable ports in Figure 3, may be arranged at an input side of the delay elements.

As shown by a signal summing interface 401 , the signals to be combined in the summation sub-unit 308 may be taken after a discrete delay given by how the switchable ports in the first and second groups A,B are set. As mentioned, it is preferred that only one switch in each group A,B is active, i.e. on, at time.

Figure 5 illustrates a more detailed implementation of the controllable delay unit according to Figure 4. As mentioned above, the same reference numerals have been used to denote the same or similar feature(s).

In this example, an exemplifying controllable delay unit 500 further comprises a VGA 313 (also shown in Figure 3) for further adjustment of the amplitude slope and the phase slope.

Moreover, delay elements T are provided as an impedance matched circuit. A high impedance interface is provided for the first and second group A, B of switches as examples of the first and seconds set of ports.

Additionally, the signal summing interface 401 is a low impedance current summing interface 501 .

The embodiments are not restricted to using impedance matching, high- impedance and low-impedance interfaces exactly as described in Figure 5. These should be regarded as a practical approach of realizing the invention.

Figure 6 shows how a controllable delay unit 607, such as shown in Figure 3, 4 or 5, may be used in a feed-forward system 600. The use of the controllable delay unit in conjunction with a vector modulator provides full control of amplitude and phase over the channel, including the linearization bandwidth needed for cancelling non-linearities of a power amplifier 603.

The feed-forward system 600 has an input port 601 and an output port 602. Furthermore, the feed-forward system 600 comprises the power amplifier 603 operatively connected to the input port 601 . The frequency range of the controllable delay unit 607 may be at least as wide as an operational bandwidth of the power amplifier 603. Moreover, the feed-forward system 600 comprises an error extractor 604 operatively connected to the power amplifier 603 and the input port 601 .

Alternatively, a reference signal, such as the input signal of the input port 601 before amplification of the power amplifier 603, may be obtained from a separate analogue- to-digital converter (not shown) which receives the desired signal.

The feed-forward system 600 comprises a vector modulator 605 operatively connected to the error extractor 604.

Furthermore, the feed-forward system 600 comprises an adder 606

operatively connected to the vector modulator 605 and the power amplifier 603.

The feed-forward system 600 comprises a controllable delay unit 607 according to embodiments herein. The controllable delay unit 607 may be operatively connected to the vector modulator 605 and the adder 606. In other examples, the vector modulator 605 and the controllable delay unit 607 may change position, i.e. the controllable delay unit 607 is operatively connected to the error extractor 604 and the vector modulator 605 is operatively connective to the controllable delay unit 607.

From a functional perspective, the controllable delay unit 607 may be seen comprising a delay adjuster 607a and a slope adjuster 607b. However, as illustrated herein these functions are performed within one block without separation, i.e. the controllable delay unit 607 performs both of these functions.

It shall be understood that feed-forward systems may be implemented in many various manner.

Nevertheless, in this example, the feed-forward system 600 further comprises an Error Power Amplifier (EPA) 608 for amplification of the extracted error signal. The amplification is set to match the error of the input signal after the power amplifier 603 such as to completely cancel the error.

Moreover, the feed-forward system 600 comprises a delay filter 609, which provides a coarse delay matching of the signal including the error and an extracted error signal in the lower branch of the feed-forward system 600.

Furthermore, this exemplifying feed-forward system 600 comprises an isolator 610, such as a circulator. The isolator may prevent transmitted signals from being reflected back into the power amplifier 603. In Figure 7, an exemplifying, schematic flowchart of the method performed by the controllable delay unit 300 of Figure 3.

As mentioned, the controllable delay unit 300 performs a method for managing an amplitude slope of an input signal 310 and a phase slope of the input signal 310 over a frequency range.

The following actions may be performed in any suitable order. Action 701

The controllable delay unit 300 receives the input signal 310.

Action 703

The controllable delay unit 300 discretely delays the input signal 310 to provide a first discretely delayed signal and a second discretely delayed signal. Action 703

The controllable delay unit 300 combines the first and second discretely delayed signals into an output signal 31 1 , wherein a gain slope of the output signal 31 1 is dependable on a difference between delay of the first discretely delayed signal and the second discretely delayed signal and the phase slope of the output signal 31 1 is dependable on combined delay of the first and second discretely delayed signals.

Action 704

The controllable delay unit 300 controls, based on a control signal 312 for setting the gain slope and phase slope of the output signal 31 1 , a first and a second set of switchable output ports of a delay chain 303 for providing the discretely delayed first and second signals, wherein at least one of the switchable output ports of the first set 306 is switched on and at least one of the switchable output ports of the second set 307 is switched on.

Action 705

The controllable delay unit 300 sends the output signal 31 1 to an output port

302.

These actions may be performed repeatedly until the desired amplitude slope and phase amplitude slope is obtained.

In some examples, software, e.g. a computer program, an application or the like, may be used to repeatedly perform these actions. With a proper algorithm in the software, the output signal 31 1 may be adjusted to exactly match a desired output signal. The proper algorithm may be e.g. a proportional-integral-derivative algorithm, or the like, known from the field of control engineering.

Figure 8 shows an example of how to implement one of the delay elements T. The sets of ports 306, 307 are exemplified as transistor switches OUT A1 , OUT_1 B, OUT_2A and OUT_2B. With at least two delay elements a minimum number of ports may be six ports, out of which there are three ports in each of the first and second set. The delay elements are preferably bridged-T types of constant- R delay circuits, consisting of coupled inductors and capacitors (shown to the right in the Figure). A balanced version is also shown to the left in the figure, which allows the complete implementation to utilize differential signals. This is a way of reducing cross-talk and frequency ripple in a real application. The high-ohmic interface can easily be implemented with small emitter followers just "sniffing" the voltage of the impedance matched delay circuit. The switches, not shown, can be implemented in many ways but common base transistor configurations usually provide good isolation. The switching action is simply done by disabling or enabling the DC current in each of the transistor circuits. Connecting many transistor based switches together increases load capacitance of the current summing network. A good approach to keep impedance low in this interface is to use active cascodes.

As used herein, the term "processing sub-unit" may in some examples refer to a processing circuit, a processing unit, a processor, an Application Specific integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or the like. As an example, a processor, an ASIC, an FPGA or the like may comprise one or more processor kernels. In these examples, the processing module is thus embodiment by a hardware module. In other examples, the processing module may be embodied by a software module. Any such module, be it a hardware, software or combined hardware-software module, may be a determining means, estimating means, capturing means, associating means, comparing means, identification means, selecting means, receiving means, sending means or the like as disclosed herein. As an example, the expression "means" may be a module or a unit, such as a determining module and the like correspondingly to the above listed means.

As used herein, the expressions "adder", "combining unit", "combining sub- unit", "summation (sub-)unit" are used to refer to a unit that is capable of adding two signals together to form one combined signal comprising said two signals.

As used herein, the term "memory" may refer to flash memory, random access memory (RAM), memory blocks of an ASIC or the like.

As used herein, the terms "number", "value" may be any kind of digit, such as binary, real, imaginary or rational number or the like. Moreover, "number", "value" may be one or more characters, such as a letter or a string of letters, "number", "value" may also be represented by a bit string.

As used herein, the expression "in some embodiments" has been used to indicate that the features of the embodiment described may be combined with any other embodiment disclosed herein.

Even though embodiments of the various aspects have been described, many different alterations, modifications and the like thereof will become apparent for those skilled in the art. The described embodiments are therefore not intended to limit the scope of the present disclosure.