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Title:
METHOD FOR CONTROLLING AN UNWANTED TIMING OFFSET INTRODUCED IN SAMPLES GENERATED BY PLURAL SAMPLE RATE CONVERSION MODULES
Document Type and Number:
WIPO Patent Application WO/2014/195757
Kind Code:
A1
Abstract:
The present invention concerns a method for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules of a radio receiving and/or transmitting device, the radio receiving and/or transmitting device interrupting the reception and/or the transmission with one radio access technology during a predetermined time duration, the said method causing the device to perform: - obtaining a system period, - defining a time duration for the interruption, based on an integer multiple of the system periods and shorter than the predetermined interruption duration.

Inventors:
BELAICHE VINCENT (FR)
PAQUELET STÉPHANE (FR)
CHRISTIN ANTOINE (FR)
Application Number:
PCT/IB2013/001716
Publication Date:
December 11, 2014
Filing Date:
June 04, 2013
Export Citation:
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Assignee:
BROADCOM CORP (US)
BELAICHE VINCENT (FR)
PAQUELET STÉPHANE (FR)
CHRISTIN ANTOINE (FR)
International Classes:
H04L7/00; H04L25/05; H04B1/40; H04W88/06
Foreign References:
US20080242347A12008-10-02
US20100135275A12010-06-03
US20120224518A12012-09-06
Other References:
TIM HENTSCHEL ET AL: "Sample Rate Conversion for Software Radio", IEEE COMMUNICATIONS MAGAZINE, IEEE SERVICE CENTER, PISCATAWAY, US, vol. 38, no. 8, 1 August 2000 (2000-08-01), pages 142 - 150, XP011091342, ISSN: 0163-6804
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Claims:
CLAIMS

1/ A method for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules of a radio receiving and/or transmitting device, the radio receiving and/or transmitting device interrupting the reception and/or the transmission with one radio access technology during a predetermined time duration, the said method causing the device to perform:

- obtaining a system period,

- defining a time duration for the interruption, based on an integer multiple of the system periods and shorter than the predetermined interruption duration.

21 A method according to claim 1 , wherein the system period is defined as a multiple of the least common multiple of the sample period at the input of the first sample rate conversion module and at the sample period at the output of the last sample rate conversion module.

3/ The method according to claim 1 or 2, wherein the system period is further defined as the least common multiple of the sample periods at the input of each of the plural sample rate conversion modules of the plural sample rate conversion modules and the sample period at the output of each of the sample rate conversion modules of the plural sample rate conversion modules.

4/ The method according to any of claims 1 to 3, wherein the system period is defined as a multiple of a period of a time base used for triggering sampling and/or a timing of a first sampling clock front.

5/ The method according to any of the claims 1 to 4, wherein the reception/transmission is interrupted for enabling the radio receiving and/or transmitting device to switch to a second radio access technology.

6/ The method according to any of the claims 1 to 5, the method further comprises: - interrupting the providing of samples to the first sample rate conversion module of the plural sample rate conversion modules, the plural sample rate conversion modules forming a chain of sample rate conversion modules,

- counting samples output by the last sample rate conversion module of the chain of sample rate conversion modules until none of the plural sample rate conversion modules of the chain of sample rate conversion modules produce any output samples

and wherein said time duration for interruption is further dependent on the number of counted samples.

7/ The method according to claim 6, the method further comprises discarding the counted output samples.

8/ The method according to claim 7, the method further comprises discarding output samples that are provided between the end of the reduced switching time duration and the end of the predetermined time duration.

91 The method according to any of the claims 7 to 8, the method further comprises:

- storing, prior to the interruption duration, values of counters and/or pointers that are used to control when and how output of the sample rate conversion modules can be computed and produced from input samples,

- restoring the stored values of counters or pointers after the interruption duration.

10/ The method according to any of the claims 1 to 5, the method further comprises:

- waiting for an occurrence of the system period during the predetermined time duration,

- determining the last occurrence of the system period during the predetermined time duration,

and reducing the predetermined interruption duration to the time period from the waited occurrence of the system period until the last occurrence of the system period. 11/ The method according to claim 10, the method further comprising: discarding samples output by the last sample rate conversion module of the plural sample rate conversion modules prior to the waited occurrence of the system period. 12/ The method according to claim 9 or 11, the method further comprising: discarding samples output by the last sample rate conversion module of the plural sample rate conversion modules between the last determined occurrence of the system period and the end of the predetermined time duration. 13/ An apparatus for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules of a radio receiving and/or transmitting device, the radio receiving and/or transmitting device interrupting the reception and/or the transmission with one radio access technology during a predetermined time duration, the apparatus comprising circuitry causing the apparatus to perform:

- obtaining a system period,

- defining a time duration for the interruption, based on an integer multiple of the system periods and shorter than the predetermined interruption duration. 14/ Apparatus according to claim 13, said apparatus further comprising circuitry causing the apparatus to define the system period as a multiple of the least common multiple of the sample period at the input of the first sample rate conversion module and at the sample period at the output of the last sample rate conversion module, 15/ Apparatus according to claim 13 or 14, said apparatus further comprising circuitry causing the apparatus to define the system period as the least common multiple of the sample periods at the input of each of the plural sample rate conversion modules of the plural sample rate conversion modules and the sample period at the output of each of the sample rate conversion modules of the plural sample rate conversion modules.

16/ Apparatus according to any of the claims 13 to 15, said apparatus further comprising circuitry causing the apparatus to define the system period as a multiple of a period of a time base used for triggering sampling and/or a timing of a first sampling clock front.

17/ Apparatus according to any of the claims 12 to 16, said apparatus further comprising circuitry causing the apparatus to interrupt the reception/transmission for enabling the radio receiving and/or transmitting device to switch to a second radio access technology.

18/ Apparatus according to any of the claims 12 to 17, said apparatus further comprising circuitry causing the apparatus to perform:

- interrupting the providing of samples to the first sample rate conversion module of the plural sample rate conversion modules, the plural sample rate conversion modules forming a chain of sample rate conversion modules,

- counting samples output by the last sample rate conversion module of the chain of sample rate conversion modules until none of the plural sample rate conversion modules of the chain of sample rate conversion modules produce any output samples

and wherein said reducing of the predetermined interruption duration to a time duration which is equal to a multiple of the system period is further dependent on the number of counted samples.

19/ The apparatus according to claim 18, said apparatus further comprising circuitry causing the apparatus to discard the counted output samples. 20/ The apparatus according to claim 19, said apparatus further comprising circuitry causing the apparatus to discard: output samples that are provided between the end of the reduced switching time duration and the end of the predetermined time duration. 21/ The apparatus according to any of the claims 19 to 20, said apparatus further comprising circuitry causing the apparatus to perform:

- storing, prior the interruption duration, values of counters or pointers that are used to control when and how output of the sample rate conversion modules can be computed and produced from inputs samples, - restoring the stored values of counters or pointers after the interruption duration.

22/ The apparatus according to any of the claims 13 to 17, said apparatus further comprising circuitry causing the apparatus to perform:

- waiting an occurrence of the system period during the predetermined time duration,

- determining a last occurrence of the system period during the predetermined time duration,

and reducing the predetermined interruption duration to the time from waited occurrence until the last occurrence.

23/ The apparatus according to claim 22, said apparatus further comprising circuitry causing the apparatus to discard samples output by the last sample rate conversion module of the plural sample rate conversion modules prior to the waited occurrence of the system period.

24/ The apparatus according to any of the claims 21 to 23, said apparatus further comprising circuitry causing the apparatus to discard samples output by the last sample rate conversion module of the plural sample rate conversion modules between the last determined occurrence of the system period and the end of the predetermined time duration.

25/ A computer program comprising program code instructions for performing the method according to any one of claims 1 to 12.

26/ Information storage means which store a computer program comprising program code instructions which can be loaded in a programmable device for implementing the method according to any one of claims 1 to 12, when the program code instructions are run by the programmable device.

Description:
Method for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules

The present invention generally relates to design of multi-mode radio frequency integrated circuit (RFIC) and more particularly it presents a method to control an unwanted timing offset introduced in the generated stream of samples in a sample rate converter at least a part of which is shared between different radio access technologies and/or different reception frequencies. Such unwanted timing offset may be introduced in the sample rate converter of a radio receiving device using a first radio access technology (RAT) at a first frequency when the reception is interrupted in order to switch temporarily to a second frequency of the first radio access technology or to a second radio access technology.

A radio access technology in this document refers to standards related to wireless cellular telecommunication networks like for example UMTS FDD (Universal Mobile Telecommunication System Frequency Division Duplexing), TD- SCDMA (Time Division Synchronous Code Division Multiple Access), LTE FDD (Long Term Evolution Frequency Division Duplexing), LTE TDD (Long Term Evolution Time Division Duplexing) LTE -A (LTE Advanced) or GSM (Global System for Mobile Communications), DC-HSDPA (Dual Carrier-High-Speed Downlink Packet Access) or other wireless networks, such as Wireless LAN for example.

Today, the number of standards related to wireless networks is growing rapidly meaning a demand for versatile hardware able to adapt to as many standards as possible. To handle the plurality of standards, it is possible to multiply the receiving and/or the transmitting part for the different standards. Such solution is expensive in term of silicon area needed to implement the receiving and/or transmitting parts. A less expensive solution can be achieved by designing the receiving part and the transmitting part to reuse as many hardware modules as possible for the different standards.

In order to be able to send and receive signals in multiple radio access technologies and/or multiple frequencies within same RAT, the sampling frequency of digital to analog converter of the transmitting parts and/or analog to digital converter receiving parts may need to be modified for some reason, while one still needs to maintain the same sampling rate at the output and/or the input of the modem.

In other exemplary cases, plural possible sampling frequencies may be selected for one RAT or for a given bandwidth. The sampling frequency of some components of the transmitting and/or receiving parts may need to be modified when transmission and/or reception configuration changes.

Further, new applications such as network based positioning are growing. These applications use the knowledge of the base station positions and very precise measurements of the differences of the observed times of arrival of some signals from these base stations to the mobile station, and/or of the difference of time of transmission from the mobile station to a base station relative to the time of arrival of received signal in the reversed direction.

Switching between different frequencies or radio access technologies using common receiving parts and/or sharing hardware modules or switching between different sampling frequencies could result in operations introducing a small unknown delay into the received signal, and/or transmitted signal, whichever applicable. The unknown delay causes some accuracy degradation of the time of arrival measurements needed for positioning.

It is also important to maintain sampling continuity when some transmitting parts are powered off for power saving purpose. The invention aims to solve these problems by proposing a method to manage an interruption in the reception and/or the transmission with one radio access technology or carrier frequency or a power off of transmission parts during a predetermined time duration.

The present invention may be used when the receiving part, respectively the transmitting part, shares at least one module participating in the rate conversion between the received signal, respectively the transmitted signal and the modem or when at least one module participating in the rate conversion needs to be powered off in order to save power.

The invention concerns a method for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules of a radio receiving and/or transmitting device, the radio receiving and/or transmitting device interrupting the reception and/or the transmission with one radio access technology during a predetermined time duration, the said method causing the device to perform:

- obtaining a system period,

- defining a time duration for the interruption, based on an integer multiple of the system periods and shorter than the predetermined interruption duration.

The unwanted timing offset is hard to predict because of use of different clock domains between input and output.

The invention concerns also an apparatus for controlling an unwanted timing offset introduced in samples generated by plural sample rate conversion modules of a radio receiving and/or transmitting device, the radio receiving and/or transmitting device interrupting the reception and/or the transmission with one radio access technology during a predetermined time duration, the apparatus comprising circuitry causing the apparatus to perform:

- obtaining a system period,

- defining a time duration for the interruption, based on an integer multiple of the system periods and shorter than the predetermined interruption duration.

Thus, it is possible to avoid an unwanted timing offset appearing on samples when an interruption occurs in the reception and/or the transmission with one radio access technology during a predetermined time duration.

The interruption may occur, for example, when the reception is switched to another carrier frequency or radio access technology in order to carry out measurements. The sampling frequency may also be changed as the carrier frequency or radio access technology is changed.

The transmission may be interrupted accordingly during the reception in order to avoid self-interference to the measurement carried out on the reception side. The transmission may be interrupted in order to limit interference or to free capacity to other user equipment using the same radio access technology. In such a case it is desirable not to keep the digital rate converters run on blank samples for the sole sake of sampling continuity as such dummy processing implies extra power consumption.

The present invention also concerns, in at least one embodiment, a computer program that can be downloaded from a communication network and/or stored on a medium that can be read by a computer or processing device. This computer program comprises instructions for causing implementation of the aforementioned method, or any of its embodiments, when said program is run by a processor.

The present invention also concerns an information storage means, storing a computer program comprising a set of instructions causing implementation of the aforementioned method, or any of its embodiments, when the stored information is read from said information storage means and run by a processor.

The characteristics of the invention will emerge more clearly from reading the following description of an exemplary embodiment, the said description being produced with reference to the accompanying drawings, among which:

Fig. 1 schematically represents an example of architecture of a receiving and/or transmitting device in which the present invention may be implemented;

Fig. 2a schematically represents an example of a representation of different modules comprised in a receiving chain of a receiving device in which the present invention may be implemented;

Fig. 2b schematically represents an example of a representation of different modules comprised in a transmitting chain of a transmitting device in which the present invention may be implemented;

Fig. 3 illustrates examples of sample rate conversion modules of a receiving and a transmitting chain;

Fig. 4 illustrates the time evolution of the receiving chain during inter frequency switching;

Fig. 5 discloses an example of an algorithm executed according to a first mode of realization of the present invention; Fig. 6 illustrates the temporal behaviour of the receiving chain according to the first mode of realization of the present invention;

Fig. 7 discloses an example of an algorithm executed according to a second mode of realization of the present invention;

Fig. 8 illustrates the temporal behaviour of the receiving chain according to the second mode of realization of the present invention;

Fig. 1 schematically represents an exemplary architecture of a receiving and/or transmitting device in which the present invention may be implemented.

According to the shown architecture, the receiving and/or transmitting device 10 device comprises the following components interconnected by a communications bus 101 : a processor, microprocessor, microcontroller or CPU {Central Processing Unit) 100; a RAM (Random- Access Memory) 103; a ROM (Read- Only Memory) 102; an SD (Secure Digital) card reader 104, or any other device adapted to read information stored on storage means and a wireless interface 105. Although this exemplary architecture has just one processing unit 100, the wireless device 10 may comprise more than one processing units, which may be used for different purposes and which may also be used for processing a shared process like the one described in forthcoming description of the invention, without departing from the scope of this invention.

The wireless interface 105 allows the receiving and/or transmitting device 10 to wirelessly communicate with other telecommunication devices not shown in Fig. 1.

Processing unit 100 is capable of executing instructions loaded into RAM 100 from ROM 102 or from an external memory, such as an SD card. After the receiving and/or transmitting device 10 has been powered on, the processing unit 100 is capable of reading instructions from RAM 103 and executing these instructions. The instructions form one computer program that causes processing unit 100 to perform some or all of the steps of the algorithms described hereafter with regard to Figs. 5 and/or 7.

Any and all steps of the algorithms described hereafter with regard to Figs. 5 and/or 7 may be implemented in software by execution of a set of instructions or program by a programmable computing machine, such as an application microprocessor, a DSP (Digital Signal Processor) or a microcontroller; or else implemented in hardware by a machine or a dedicated component, such as an FPGA {Field-Programmable Gate Array) or an ASIC {Application-Specific Integrated Circuit). Further, the steps of the algorithms may be executed in a device which combines software and hardware execution, for example by using hardware accelerators for some steps.

In other words, the receiving and/or transmitting device 10 includes circuitry, or a peripheral device including circuitry, causing the receiver and/or transmitter device 10 to perform the steps of the algorithms described hereafter with regard to Figs. 5 and/or 7. Such a peripheral device may be an external device connectable to the receiving and/or transmitting device 10.

Such receiving and/or transmitting device may also be installed as part of another device like a user equipment or a base station or a base station radio head. For example, the receiving and/or transmitting device 10 is in form of a chip, a chipset, or a module. Alternatively, instead of being installed in or connected to a dedicated communication device, the receiving and/or transmitting device according to the invention may provide communication capability to any suitable device, such as a computer device, a machine, for example, a vending machine, or a vehicle like a car or truck, where the device may be installed in or connected to for this purpose.

The term circuitry refers either to hardware implementation, consisting in analogue and/or digital processing, or to a combination of hardware and software implementation and/or interconnecting technology based on wiring, optical links or a combination of them. Software implementation includes instructions of a computer program associated with memories and processor causing the processor 100 to perform any and/or all steps of the algorithms described hereafter with regard to Figs. 5 and/or 7.

Fig. 2a schematically represents an example of a representation of different modules comprised in a receiving chain of a receiving device in which the present invention may be implemented.

A sample rate conversion module is a module that provides at its output a different number of samples per time period from what it receives at its input

F '

according to some sample rate conversion ratio -^, and after processing completely

F i

Mi input samples will produce a number M i+1 of output samples that depend only on

A sample rate conversion chain performs conversion from a first frequency F 0 to

p

a final frequency F n could be modelled as a multiplication by a fraction— , where

F 0 p

fraction— is a rational number.

The overall conversion ratio between the sample rates F n and F 0 at output and input of the receiving and/or transmitting chain can be decomposed to a multiplication of one or several ratios:

Fo F 1 F-n-l

The ratio between F n and F 0 is a rational number, which may have a large numerator and denominator.

This equation leads to an implementation like illustrated Fig. 2a where the sample rate conversion is decomposed into a plural sample rate conversion modules 201 to 204, each one being responsible for a sample rate conversion from frequency F t

F ' P '

to frequency F i+1 corresponding to a fraction - ± =— , where P £ and Q t are prime

F i Qi

together. P £ and Q t are prime together if the ratio Pi/Qi cannot be simplified or if their greatest common divisor is one. For example and in a non- limitative way, a sample rate conversion chain may comprise a digital filter like a CIC filter, which may do up sampling at input and/or down sampling at output, a Farrow structure, a serial to parallel converter, a parallel to serial converter, a high speed serial digital interface between a base band integrated circuit (BBIC) and a radio frequency integrated circuit (RFIC) or an interpolation module.

At least a part of above mentioned examples can consist in one sample conversion module or be decomposed into plural sample rate conversion modules.

A sample rate conversion module could be seen as a finite state automaton working cyclically. The internal state of the automaton is defined by an index.

In such system we define what we call the system period or II sys of the receiving and/or transmitting chain.

This system period is defined by the following equation:

Where a \l b denotes the least common multiple of a and b. The system period corresponds to the least common multiple of the inverse of the frequencies F £ .

In an alternative embodiment of the invention, the sampling clock at F 0 used in the ADC (analogue to Digital Converter) of the reception chain, resp. DAC (Digital to Analogue Converter) of the transmission chain, is discontinued during the gap. On the other hand, the RFIC has a local time base with a clock at F LTB which is maintained across the gap, and the sampling clock is generated so that its first cycle is quite close to a defined clock cycle of the local time base clock at F LTB , that is to say this cycle is defined because it can be programmed in an event generator based on a time counter running on the same clock at F LTB . In such a case the present invention ensures that the system period is an integer count of the sampling clock by defining II sys as:

In an alternative embodiment the timing accuracy is obtained with a slight degradation but with the benefit of having a shorter system period by considering only the sample rates at input and at output of conversion chain, i.e.:

In an alternative embodiment we combine the aspect of the two previous alternative embodiments, i.e.:

Finally, in an alternative embodiment the system period is n sys is a multiple of any of the system period value of the previous embodiments with the benefit of having a longer system period, which may allow easier real time control of input sampling start and stop relative to a well-defined system period boundary.

We distinguish the two following types of states for a sample rate conversion module:

• a "data state", that indicates which sample values are stored in the FIFO (First In First Out) memory of the sample rate conversion module, and

• a "control state", that indicates the state of the FSM (Finite State Machine) controlling the sample rate conversion module. This state is defined for instance by any pointer and/or counter in input and/or output buffers and allows to decide to trigger some output samples after a number of input samples is received at input. Similarly we denote by data state of the system the set of all data states of all sample rate conversion modules in the receiving and/or transmitting chains and by control state of the system the set of all control states of all sample rate conversion modules units in the receiving and/or transmitting chains.

The receiving and/or transmitting chains have a "coherent" control state, or are in a "coherent state", when all the sample rate conversion modules are starved, that is to say when, based on its available input, no sample rate conversion module is able to produce any output.

It can be proven that the system period is the time for the control state of said sample rate conversion modules to move from a state to the same state. For example, the system is in a coherent state at time instant t 0 and is at the same coherent state at a time t-L such that t — t 0 is a multiple of n sys , that is to say the number of input samples at F 0 from t 0 to t is a multiple of F 0 x n sys .

If the sample rate conversion modules would have their input stopped at some input sample received at time to and then go to coherent state "S", then for any input sample received at time such that ti > t 0 and (t 1 - t 0 ) x F 0 is a multiple of Fo x n sys , if the input is stopped there, then the same coherent state S is reached.

It should be noted that the receiving chain of the invention illustrated by Fig. 2a is naturally driven by its input that is sampled at F 0 , so time instants t 0 and t naturally translate to respective samples numbered t 0 x F 0 and t x F 0 . Instead the transmitting chain of the invention illustrated by Fig. 2b is timed by output: in such a case we implicitly assume that digital to analog converter reads from a FIFO the input of which is the output of the rate conversion chain, and that the occupancy level of this FIFO crossing hysteresis thresholds serves as flow control command to the input of the rate conversion chain. This way, the rate conversion chain is still driven by its input and the same reasoning applies for the reception, except that time instants t 0 and t-L have to be understood as virtual time instants referring to input samples on a time scale at F 0 , rather than time instant on the digital to analog sampling clock F n .

In the example of Fig. 2a, plural sample rate conversion modules 201 to 204 of a receiving unit are shown.

The RFIC part 200 is composed of plural sample rate conversion modules 201 , 202 and 203. The BBIC part 206 is composed of a sample rate conversion module 204 and a modem 205. Only four sample rate conversion modules 201 and 204 are shown in Fig. 2a for the sake of simplicity. It has to be noted here that according to the present invention, the modem 205 for the reception unit is downstream of the sample rate conversion module 204 of Fig. 2a, i.e. the sample rate conversion module 204 is the last sample rate conversion module before the modem 25.

It has to be noted here that the sample rates conversion modules 201 to 204 form a chain of sample rate conversion modules. The present invention is also applicable when at least two sample rate conversion modules operate in parallel.

For example, the sample rate conversion module 201 is a cascaded integrator- comb (CIC) filter which is modeled as being composed of a CIC buffer fill 201a, a CIC buffer dump 201b and a CIC filter 201c. Up-sampling by a factor P can be obtained by inserting P— 1 zero samples every input sample. A CIC filter is an optimized class of finite impulse response (FIR) filter combined with an up-sampler and a decimator. For example, the sample rate conversion module 201 is an optimized implementation of a FIR with up sampling at input and down sampling at output. The sample rate conversion module 202 is for example channel filter, the sample rate conversion module 203 is for example a frame builder and the sample rate conversion module 204 is a frame de -builder.

Some sample rate converters may not be "sample rate conversion modules" in the sense of the present invention to the extent that they work on a block by block basis rather than outputting sample as soon as possible based on the only input samples on which their value depend, where "as soon as possible" means that when the input is stalled

after M t input samples are input, then the output is not stalled as long as the count M i+1 of output samples not needing one more input sample is reached, with M i+1 reminded in the formula below:

Fig. 2b schematically represents an example of a representation of different modules comprised in a transmitting chain of a transmitting device in which the present invention may be implemented.

The RFIC part 250 is composed of plural sample rate conversion modules 251 , 252 and 253. The BBIC part 256 is composed of a modem 205 and sample rate conversion module 254. Only four sample rate conversion modules 251 and 254 are shown in Fig. 2b for the sake of simplicity. It has to be noted here that according to the present invention, the modem 205 for the transmission unit is upstream of the sample rate conversion module 254 of Fig. 2b, i.e. the sample rate conversion module 244 is the first sample rate conversion module after the modem 205 and the sample rate conversion module the last sample rate conversion module of the transmission chain.

It has to be noted here that the sample rates conversion modules 251 to 254 form a chain of sample rate conversion modules.

The present invention is also applicable when at least two sample rate conversion modules operate in parallel.

Fig. 3 illustrates examples of sample rate conversion modules of a receiving chain.

The rows noted 300, 301 and 302 represent the different sub sample rate conversions 201a, 201b and 201c performed in the CIC filter 201.

The sampling frequency at the input of the CIC filter is equal to 48 MHz.

A first sub sample rate conversion with a ratio P;/Qi of 1/5 is performed on the sampling frequency of 48 MHz by the CIC buffer fill 201a, a second sub sample rate conversion with a ratio P;/Qi of 5/1 is performed on the sampling frequency of 9.60 MHz by the CIC buffer dump 201b and a third sub sample rate conversion with a ratio Pi/Qi of 4/5 is performed on the sampling frequency of 48 MHz. The sampling frequency at the output of the CIC filter 201 is equal to 38.4 MHz.

The sample rate conversion module 201 is followed by the sample rate conversion module 202.

The second sample rate conversion module 202 performs a sample rate conversion with a ratio Pi/Qi of 4/5 on the sampling frequency of 38.4 MHz. The sampling frequency at the output of the second sample rate conversion module 202 is equal to 30.72 MHz.

The second sample rate conversion module 202 is followed by the third sample rate conversion module 203.

The third sample rate conversion module 203 performs a sample rate conversion with a ratio Pi/Qi of 1/24 on the sampling frequency of 30.72 MHz. The "sampling frequency" at the output of the third sample rate conversion module 203 is equal to 1.28 MHz, to the extent that a "sample" is a frame containing several samples. This framing is useful only for the inter-chip communication and has no added value in terms of signal processing. The third sample rate conversion module 203 is followed by the fourth sample rate conversion module 204.

The fourth sample rate conversion module 204 performs a sample rate conversion with a ratio Pi/Qj of 24/1 on the sampling frequency of 1.28 MHz to the extent that it carries out frame de-building.

It has to be noted here that a conversion ratio may be equal to 1/1 according to particular configuration. The sampling frequency at the output of the fourth sample rate conversion module 204 is equal to 30.72 MHz.

According to the example of Figs. 2 and 3, the system period is then equal to (25/16) i.e. approximately 1.56 micro seconds, when the system period is computed by the formula:

In this example, the final sample rate corresponds to the target sample rate output from module 204 that is finally input to the modem.

Fig. 4 illustrates the temporal characteristics of the reception chain during an inter frequency switch.

Inter frequency switching from a first frequency carrier or radio access technology (RATI) to a second frequency carrier or radio access technology (RAT2) is performed in order to perform measurements at the second frequency carrier or radio access technology (RAT2), which is different from the one currently used for receiving signal. A gap may also appear when at least one of the receiving and/or transmitting chains is partially powered off in order to reduce power consumption.

The example of Fig. 4 will be disclosed in an example wherein an inter frequency measurement is carried out.

Considering that the device 10 is currently operating using RATI , referenced

40, it occurs that the device 10 should sometimes change RAT to perform some measurements based on signalling provided by the network. One typical example of this is the measurement of its radio environment. To do this, the device 10 toggles to a second carrier frequency or radio access technology, RAT2 referenced 41 to perform the signalled measurement. When these measurements are completed, the receiver 10 toggles back to the serving RAT, RATI referenced 42. For example, the network triggers the measurements by sending a request to the device 10 to perform one or a plurality of measurements at different times. The request contains the moment and the duration allowed for the measurement or measurements. In a variant the receiver 10 may decide at what time the measurement or measurements may be performed.

It is to be understood that this is only an example of such switching between two different RATs. On the other hand, there may be an interruption in RATI reception for other reasons, such as discontinuous reception.

The switching implies a gap, referenced 48. The switching between RATI to RAT2 and RAT2 to RATI can't be instantaneous because some hardware resources are reused for receiving RAT2 and some time may be needed to program the parameters related to the reception of RAT2. Notable examples of these parameters are the centre frequency and/or the width of the frequency band associated with RAT2. A receiver switching time is therefore necessary between each RAT to reprogram the different modules of the receiving chain. This is illustrated by the first receiver switching time 44 for the switching between the RATI reception 40 and the measurement RAT2 41. A second receiver switching time 46 is also introduced between the measurements RAT2 41 and RATI reception 42.

During a carrier frequency switching, sampling frequencies of at least a part of the sample rate conversion modules 201 to 204 may need to be changed in order to comply with the desired sample rate at the input of the modem 205, since the targeted sample rate at the input of the modem depends on the used wireless communication standard and even within the same standard the targeted sample rate could also depend on the frequency band, bandwidth and/or different modulations used in the RAT or RATs.

The RATI 40 is interrupted in order to allow the measurement to take place, and when this happens, the system control state is unknown. Since the sample rate conversion modules 201 to 204 are shared between the different RATs, at least one sample rate conversion module 201 to 204 is reprogrammed to fit the needs of the measurement RAT2 41. At the end of the measurement for RAT2 41, the at least one sample rate conversion module 201 to 204 is reprogrammed to fit the needs of RATI 42 again. Doing so, there is no continuity in the sample rate conversion between the first occurrence of RATI 40 and the second occurrence 42. This interruption and reset of the sample rate control state at arbitrary time is introducing an unwanted timing offset in the timing of the output stream of samples for the RATI .

This unwanted timing offset may introduce degradation of modulation/demodulation quality in the receiving and/or transmitting chain. This unwanted timing offset brings also timing inaccuracy when the device 10 implements global positioning system using Observed Time Difference of Arrival (OTDoA) or Enhanced Cell Id (E-CID). OTDoA aims at computing very precise location based on observed time difference of arrival of signals between the device 10 and a plurality of base stations. It needs an accurate measurement of the difference between the times of arrival of several signals. Also for E-CID timing accuracy is important both on the uplink to and the downlink from the serving base station. The unwanted timing offset introduced by the interruption and the sampling frequencies change of at least a part of the sample rate conversion modules 201 to 204 threatens this accuracy.

Fig. 5 discloses an example of an algorithm executed according to a first mode of realization of the present invention.

The present algorithm is disclosed in an example wherein a change from RATI to RAT2 is performed in order to perform measurements on RAT2. The present algorithm may be also executed for other purposes as already stated.

At step S50, a request for a change of RAT is detected. This request may be triggered by the network or by the device 10. The duration of the change of RAT is predefined or indicated by the network.

At next step S51, providing input samples at the input of the first sample rate conversion module processing received signal is interrupted.

At next step S52, an output sample counter is activated. The output sample counter counts the number of received samples which are output by the last sample rate conversion module 204 of the receiving chain, starting from the first sample inside the gap, this sample and the subsequent ones are discarded.

It has to be noted here that the step S52 may be executed prior to or at the same time as step S51.

At next step S53, processing unit 100 waits that the all chain of sample rate conversion modules get starved, i.e. that there is no more input sample at the input of any sample rate conversion module. If that time duration cannot be determined accurately, processing unit 100 may wait for a predetermined time duration which guarantees that all sample rate conversion modules get starved. After this step, based on their available inputs and respective control states, no sample rate conversion module is able to produce any output.

At next step S54, the values of controls states of the sample rate conversion modules are stored. The time period corresponding to the number of output samples counted in step S52 multiplied by the output sample period is denoted with 63 in Fig. 6.

Fig. 6 illustrates the behaviour in the time of the receiving chain according to the first mode of realization of the present invention.

In Fig. 6, samples at modem 205 put in for RATI are denoted 60 and 62 and samples for RAT2 are denoted 61. The predefined duration of the change of RAT or the duration indicated by the network is referenced with 65. It has to be noted here that RATI 60 ends after beginning of the duration indicated by the network 65 in order to make sure that before gap no output samples provided by the reception chain are missed, and RATI 62 starts slightly before the end of the predefined duration of the change of RAT or the duration indicated by the network 65, so that it can be ensured that receive chain is initialized, i.e. that first output samples at the end of period 64 corresponding to initialization transients are trashed.

At next step S55, an envelope of the duration of activity of RAT2 is determined as to be equal to an integer number of system periods. The duration of activity of RAT2 is typically shorter than the envelope duration activity of RAT2 because time may still be necessary to re-configure receiving chain components on RAT2 i.e. re- tune a Radio Frequency synthesizer, re-initialize digital filters etc. when all these tasks cannot fit into period 63. The envelope of the duration of activity of RAT2 is for example the maximum number of system periods that can be obtained within a time period which is equal to the difference between:

• the predefined duration of change of RAT or the duration indicated by the network noted 65 in Fig. 6.

• minus period 63 which equals to the number of output samples counted from step S52 multiplied by the output sample period.

· minus some minimum re-start time that is a tailing period referenced with 64, the minimum re-start time being needed for transient erasure when reception RATI is re-started 62.

The determined envelope of the duration of activity of RAT2 is referenced as 66 in Fig. 6. The starting instants at the output of the rate conversion module 204 of the system periods within the envelope of the duration of activity of RAT2 are denoted 67a to 67f in Fig. 6.

The starting instants at the input of the rate conversion module 201 of the system periods within the envelope of the duration of activity of RAT2 are referenced 68a to 68f in Fig. 6.

It has to be noted here that the time duration 64 in Fig. 6 corresponds to the difference between the time duration 65 and the sum of time duration 66 and of the time duration 63.

At next step S56, the activity of RAT2 is performed and the count of discarded samples from beginning step S52 up to end of step S53 is read to know how long period 63 is.

At next step S57, a number N res tart of output samples to be trashed at re-start of RATI is computed and the reception of RAT2 is stopped. The reception of RATI is re-started, and re-tuning the RF to the carrier frequency of RATI , i.e. setting the gains, filters and so on, is performed. The first RATI input sample provided to the first sample rate conversion module 201 corresponds to the end of last system period 68f at input. The values of the control states of the sample rate conversion modules are restored. The output samples obtained during this re-starting are trashed until number of trashed sample reaches N res tart. This corresponds to samples discarded during time duration 64.

Next step S58, comprises the fmalization of switching from RAT2 to RAT 1 which consists of stopping trashing of output samples of last sample rate conversion module in the change, and delivering the output samples to the modem input. More precisely, while switching to RATI is effective at modem input from end of period 64, switching of Radio frequency components to RATI typically begins during end of period 61 before end of last system period 67f, and may be complete before or during period 64, and analogue to digital sampling of RATI starts at 68f.

Fig. 7 discloses an example of an algorithm executed according to a second mode of realization of the present invention.

In the second mode of realization, the system periods are monitored at the input of the sample rate conversion module 201 and at the output of the sample rate conversion module 204 continuously since the initial start of reception of RATI . The present algorithm is disclosed in an example wherein a change from RATI to RAT2 is executed in order to perform measurements on RAT2. The present algorithm may be also executed for other purposes as already stated.

At step S70, a request for an interruption of reception, for example a change of RAT is detected. This request may be triggered by the network or by the device 10 and comprises the start instant t 0 referred at modem input of the interruption. The duration 85 of the change of RAT is predefined or indicated by the network.

At next step S71, processing unit 100 determines a timing offset τ 0 which is equal at least to the opposite of transient time of the sample rate conversion module plus some margin which is sufficient for nominal time t 0 + τ 0 for closing the input:

• not being too early and loosing wanted samples, and

• not being too close to a system period boundary at the input of the sample rate conversion module 201, as this would create some ambiguity since real time instant for closing the input may depart from nominal time due to timing inaccuracy when crossing clock domains from output rate conversion module 204 to input of the rate conversion module 201.

In the case that t 0 + τ 0 would be too close to a system period boundary and cause an ambiguity due to asynchronism, a little longer τ 0 time is taken.

At next S72, a request for an interrupt of the providing of input samples at the input is received from the output of the sample rate conversion module 204.

At next step S73, the next system period that occurs after the end of RAT period 80 is waited for. In the second mode of realization of the present invention, the system period is monitored continuously. The next system period is denoted 87b in Fig. 8.

It has to be noted here that if the next system period is close to the end of RATI, the following system period is waited for.

Fig. 8 illustrates the behaviour in the time of the receiving chain according to the second mode of realization of the present invention.

In Fig. 8, RATI is denoted 80 and 82 and RAT2 is referenced with 81.

The starting instants of system periods at the output of the sample rate conversion module 204 are denoted 87a to 87g. The predefined duration of the change of RAT or the duration indicated by the network is denoted 85.

The starting instants of system periods at the input of the sample rate conversion module 201 are denoted 88a to 88f. It has to be noted here that RATI 80 ends only after beginning of the duration indication by the network 85 in order to make sure that no output samples provided by the reception chain are missed, and RATI 82 starts before the end of the predefined duration of the change of RAT or the duration indicated by the network 85 in order to make sure that receive chain is initialized, i.e. that first output samples corresponding to initialization transients are trashed.

At next step S75, an envelope of the duration of activity of RAT2 is determined as to be equal to an integer number of system periods. The duration of activity of RAT2 is equal to the envelope duration activity of RAT2 minus the time necessary to re-configure receiving chain components on RAT2 i.e. re-tune a Radio Frequency synthesizer, re-initialize digital filters and so on. The envelope of the duration of activity of RAT2 duration of activity of RAT2 is for example the maximum number of system periods that can be obtained within a time period which is equal to the difference between

· the predefined duration of change of RAT or the one indicated by the network, denoted 85 in Fig. 8.

• minus the time from beginning of that predefined duration to the next unambiguous system period boundary.

• minus some minimum time needed to erase transients at re-start of reception of RATI .

The envelope of the duration of activity of RAT2 is therefore the maximum number of system periods that can be obtained within a time period between the end of system period 87b and some instant 87g sufficiently before the end of 85 for RATI transient erasure.

The determined envelope of the duration of activity of RAT2 is denoted 86 in

Fig. 8.

In an alternative mode of realization, at step S71 , when t 0 + τ 0 is too close to a system period boundary which creates ambiguity due to asynchronism, τ 0 is not taken a little bit longer to avoid this ambiguity, instead system periods are counted with a toggling one bit counter, and after stopping the input it is checked whether stopping happened at the end of an odd period or of an even period. Hence, at step S75, the envelope of the duration of activity of RAT2 is decreased or not by one system period depending whether t 0 + τ 0 was detected to fall after or before the too close system period boundary, i.e. whether the input was closed on the too close system period boundary or on the next one.

According to the example of Fig. 8, the system period boundary 87g is the last system period that occurs before the end of the time period 85. It may also be an earlier system period boundary depending on the minimum time needed to warm-up for re-starting reception of RATI.

At next step S76, the activity of RAT2 is performed within the envelope of the duration 86.

At next step S77, a number N res tart of samples to trash at re-start of RATI is determined. Determining N res tart amounts to determining system period boundary 87g that ends the envelope of the duration of activity of RAT2, as N re start/F n is the duration 84. The number N res tart is how many samples need to be erased and it depends on the minimum time needed to warm-up for re-starting reception of RATI, i.e. on how long the start transient to erase is, and on how far the system period boundary at (87g) is from the end of time duration 85. The reception of RATI is re-started and the values of counters or pointers that are used to control when and how output of the sample rate conversion modules can be computed are restored. The N res tart output samples, which correspond to the time 84 elapsed from the last system period 87g and until the end of time duration 85 are discarded, where the corresponding end of system period 87g at input is the first RATI input sample after re-start.

Next step S78 comprises the fmalization of switching from RAT2 to RATI, which means that trashing output samples is stopped and outputs are delivered to the modem. More precisely, switching to RATI is effective at modem input from end of period 84, switching of Radio frequency components to RATI typically begins during end of period 81, and may be complete before or during period 84, starting analogue to digital sampling of RATI starts at the beginning of period 82.