Title:
METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN
Document Type and Number:
WIPO Patent Application WO/2016/203492
Kind Code:
A3
Abstract:
A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges to both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address register. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.
Inventors:
GYAN PRAKASH (IN)
NIDHIR KUMAR (IN)
NIDHIR KUMAR (IN)
Application Number:
PCT/IN2016/000155
Publication Date:
March 30, 2017
Filing Date:
June 14, 2016
Export Citation:
Assignee:
GYAN PRAKASH (IN)
NIDHIR KUMAR (IN)
NIDHIR KUMAR (IN)
International Classes:
G06F1/04; H04L7/02; G06F11/00
Domestic Patent References:
| WO2012013972A1 | 2012-02-02 |
Foreign References:
| US8775701B1 | 2014-07-08 |
Attorney, Agent or Firm:
PRABHU, Rakesh (IN)
Download PDF:
Previous Patent: ASYNCHRONOUS CLOCK GATING CIRCUIT
Next Patent: SYSTEM FOR AERATION AND SEPERATION OF CONTAMINANTS FROM FLOWING WATER
Next Patent: SYSTEM FOR AERATION AND SEPERATION OF CONTAMINANTS FROM FLOWING WATER