[Title of Invention]

METHOD FOR DETECTION OF MISMATCH BETWEEN PARALLEL POWER ELECTRONIC ELEMENT, POWER ELECTRONIC MODULE, COMPUTER SOFTWARE, COMPUTER-READABLE NONTRANSIENT RECORDING MEDIUM [Technical Field] [0001]

This disclosure pertains to the field of power electronic modules. More specifically, the invention is related to the monitoring of assembly containing a plurality of devices/elements in parallel.

[Background Art]

[0002]

Such power devices are submitted to high thermic changes and high thermo-mechanical stresses. Due to the wide variety in the compositions and structures of the different parts/devices constituting the assembly, crack propagation, wire-bonds lift-off, delamination, metallization reconstruction and other effects lead to failure of the interconnections. Failure mechanisms are coupled and most often result in the lift-off of wire bonds. Such failures are very difficult to predict or to detect before the general breakdown of the assembly. In addition, the ageing of parallel devices may not be uniform due to e.g. manufacturing or mounting mismatches, resulting in electro-thermo- lifetime mismatches. Knowing the state of health of each power device in an assembly is important in the operating and maintenance phases to perform respectively lifetime extension and selective maintenance/replacement.

[0003]

Monitoring the wire-bonds on-line can be performed using the steadystate voltage (referenced V _ce ) through the device at high current and to compare it to a limit. To make the V _ce specific to a single power device, the other parallel devices can be turned-off. Operating the devices one by one is possible to assess the individual degradation. However, this method requires individual drivers. The steady-state V _ce is temperature and current (including ripple) dependent and calibration/corrections must be performed. In addition, clamp circuit must be implemented to protect the measure, imposing time-responses incompatible with fast switching frequencies and/or extreme duty-cycles. Finally, the connection to the high voltage imposes high design and safety constraints making this solution difficult to adopt.

[Summary of Invention]

[0004]

This disclosure improves the situation.

[0005]

It is proposed a method for detection of a mismatch between parallel power electronic elements into a power electronic module, said method comprising: a. in response to the detection of a common turn-off of said elements, triggering a measuring period; b. during the measuring period, measuring a sequence of emitter voltages V _e E of at least one of said elements; c. extract data, from the measurements, said data including the signs and/or the amplitude of local extremums of said emitter voltage V ₆ E during the measuring period; d. deduce from the extracted data at least an existence or an absence of a mismatch between said elements.

[0006] In another aspect, it is proposed a power electronic module comprising at least two parallel power electronic elements and being arranged to implement such a method.

[0007]

In another aspect, it is proposed a computer software comprising instructions to implement at least a part of a method as defined here when the software is executed by a processor. In another aspect, it is proposed a computer-readable non-transient recording medium on which a software is registered to implement the method as defined here when the software is executed by a processor.

[0008]

The following features, can be optionally implemented, separately or in combination one with the others:

[0009]

The extracted data include at least:

- the signs of local extremums of a sequence of two emitter voltages V ₆ EI and V _e E2 of two elements, or

- the sign and the amplitude of local extremums of a sequence of emitter voltage VeE of one element; and, if a presence of a mismatch between said elements has been deduced, the method further comprising: e. deduce from the extracted data if an element of which the emitter voltage VeE, or V _e Ei and V _e E2, has been measured is, or is not, the most degraded.

[0010]

The extraction from the measurements is made by an analogic and logical circuit, such that the use of an Analog to Digital Converter is made redundant. [0011]

The extracted data further includes amplitudes of local extremums of said emitter voltage V _e E during the measuring period and, if a presence of a mismatch between said elements has been deduced, the method further comprising: f. deduce from the extracted data a quantification of said mismatch. [0012]

A differential emitter voltage V _ee of a pair of elements is measured. [0013]

Implemented on a module comprising at least three parallel power electronic elements, the measurements are made in a sequenced manner for each pair of elements with a common monitoring circuit, a multiplexer being operationally interfaced between said monitoring circuit and said elements. [0014]

The method further comprises:

- imposing a supplementary external gate resistance during the measuring operation.

[0015]

The deduction operation further comprises to identify a most degraded element among at least two elements, and then the series of operations is reiterated at least one time, the at least one reiteration including to induce a delay d of the turn-off of at least one of the elements with respect to another element before triggering the measuring period. [0016] The series of operations is reiterated at least one time such that the detection mismatch is implemented along the operational life of the module. [0017]

The method further comprises:

- generating an alert signal in function of the deduced information.

[Brief Description of Drawings]

[0018]

Other features, details and advantages will be shown in the following detailed description and on the figures, on which:

[FIG. 1]

[Fig. 1] is a sectional side view of an assembly, or module, including two parallel semiconductor devices/elements.

[FIG. 2]

[Fig. 2] is a top view of an assembly according to [Fig. 1], where “Y” is the cutting plane of [Fig. 1], [FIG. 3]

[Fig. 3] is a graphic showing the turn-off delay in function of the current flowing through a power element according to an embodiment.

[FIG. 4]

[Fig. 4] is a graphic showing the turn-off delay in function of the threshold voltage of a power element according to an embodiment.

[FIG. 5]

[Fig. 5] is a graphic showing the current flowing through two parallel power elements during a turn-off period according to an embodiment.

[FIG. 6]

[Fig. 6] shows an architecture of a power module according to an embodiment.

[FIG. 7] [Fig. 7] shows an architecture of a power module according to an embodiment.

[FIG. 8]

[Fig. 8] is a graphic showing the waveforms of the emitter voltages of two parallel power elements of a module during a turn-off period according to an embodiment.

[FIG. 9]

[Fig^ 9] is a graphic showing the superimposition of waveforms of an emitter voltage of a power element during turn-off periods according to an embodiment.

[FIG. 10]

[Fig. 10] is a graphic showing the superimposition of waveforms of an emitter voltage of a power element parallel to the power element of [Fig. 9] during the same turn-off periods according to an embodiment.

[FIG. 11]

[Fig. 11] shows schematically how to identify degraded power elements with a circuit according to an embodiment.

[FIG. 12]

[Fig. 12] is a graphic showing a maximum of emitter voltages (“peaks”) of a power element in function of its degradation counted as a number n of wires lift-off.

[FIG. 13]

[Fig. 13] is a graphic showing the superimposition of waveforms of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 6].

[FIG. 14]

[Fig. 14] is a graphic showing the superimposition of waveforms of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 7]. [FIG. 15]

[Fig. 15] is a graphic showing a minimum of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 6] according to an embodiment.

[FIG. 16]

[Fig. 16] is a graphic showing a minimum of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 8] according to an embodiment.

[FIG. 17]

[Fig. 17] is a graphic showing a maximum of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 6] according to an embodiment.

[FIG. 18]

[Fig. 18] is a graphic showing a maximum of the voltage between the emitters of two parallel power elements of a module according to an architecture of [Fig. 7] according to an embodiment.

[FIG. 19]

[Fig. 19] is a circuitry to impose a supplementary external resistance during a turn-off switching period according to an embodiment.

[FIG. 20]

[Fig. 20] is a logical diagram showing how to convert voltages offsets into delays offsets according to an embodiment.

[FIG. 21]

[Fig. 21] is a graphic showing how indexes about degradations of two parallel elements of a module can be constructed in function of the time according to an embodiment.

[Description of Embodiments]

[0019] It is now referred to [Fig. 1] and [Fig. 2]. In the following, an assembly, or a module 1 , comprises at least two parallel power electronics elements 11. A power electronic element 11 can be, for example, a power semiconductor device, a power sub-module or a power converter. Here, the words “element” or “device” are used to designate sub-part of a power “module” or power “assembly” that are electrically connected in parallel one with respect to the other. The elements 11 of the same module 1 can be packaged together or separately one from the other. [0020]

[Fig. 1] is an example of a cutting view along the line referenced “Y” of the module 1 shown on [Fig. 2]. In a various embodiment, a top side view can show elements packaged separately. The element referenced “Z” on [Fig. 2] schematically represents an electrical isolation of a configuration wherein the elements 11.1 and 11.2 are disconnected one from the other as it will be explained hereinafter with reference to [Fig. 7]. The emitter pads (el and e2) of respectively elements 11.1 and 11.2 are separated one from the other. The Gate drivers (G1 and G2) of respectively elements 11.1 and 11.2 are separated one from the other. On the contrary, in a configuration wherein the elements 11.1 and 11.2 are connected one to the other as it will be explained hereinafter with reference to [Fig. 6] (common emitter pad E and common gate driver G), the isolation Z of [Fig. 2] would be absent. By simplicity, the external connections to the system are not drawn. On another configuration, elements 11.1 and 11.2 are based in separate mechanical structures described in [Fig. 1] with external electrical connection of the elements E, gate drivers (G1 and G2) and emitter pads (el and e2). In other words, the connection of the elements can be decided and made on the system level outside the device structure. [0021]

[Fig. 1] and [Fig. 2] show an example of a module 1 including two elements 11 (distinctly referenced 11.1 and 11.2 on [Fig. 2]), and comprising a superposition of layers. From the bottom to the top, the [Fig. 1] comprises of the elements 11: an electrical insulator layer 101 (for example based on aluminum oxide) and a conductive layer 102 (for example in copper). The module 1 further comprises parts that are associated separately to each element 11, from the bottom to the top: a solder layer 103, a semiconductor die 104 and a metallization layer 105. The module 1 further comprises conductive wire bonds 2 ensuring electrical connection between a part of the conductive layer 102 and the metallization layer 105 of the element 11 of the cutting view (the module 1 comprising at least two parallel power electronics elements 11). [0022]

Each element 11 comprises, here, a semiconductor die 104 which is a semiconductor element, for example, an Insulated Gate Bipolar Transistor (IGBT) or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). It can be made of silicon, silicon carbide (SiC) and/or gallium nitride (GaN). The element 11 is a power electronic device: it is arranged to operate under a voltage superior to 50V and a current superior to 1 A.

[0023]

The semiconductor die 104 is metalized at least on one of its sides, here on its top side. In other words, the semiconductor die 104 is coated with a metallization 105. The metallization layer is, for example, made of an aluminum alloy. Such a metallization 105 has a thickness comprised between 1 and 20 micrometers. The free surface is used to fix wire bonds 2, for example by thermosonic bonding. Such a connection is subjected to hard conditions during operational life of the module 1 and some cracks and defects can appear at this specific location.

[0024]

<Theory> In a module 1 comprising at least two parallel power electronics elements 11, the load current is distributed through the various paralleled elements 11 according to their on-state resistance that is dependent on the assembly and the junction temperature. When a lift-off of the wire bonds 2 occurs, or any other electrical connection defect, an increase of the on-state electrical resistance of the element appears. When one element 11 is more degraded than the other(s) paralleled power element(s) 11 , a current reduction flowing through the one element can be observed of e.g. 1% to 20%. The current reduction is supported on the paralleled power element(s) that will conduct more current.

[0025]

Furthermore, in case of thermal degradation (generally causing delamination) the temperature on the degraded power element 11 increases, causing a reduction of the threshold voltage up to 0.5V.

[0026]

In the following, the elements 11 are IGBT devices, but any skilled person can translate the explanations based on such examples to other power electronic elements, like MOSFET or MISFET semiconductors for example. [0027]

The applicants noticed that the turn-off waveform is strongly dependent on the current flowing in the element 11. With a classical gate drive circuit imposing a voltage step from a positive voltage V _cc to a negative voltage V _ee , the gate voltage V _ge over the time t in the paralleled elements can be calculated according to the following equation [Math. 1]. The saturation collector current is dependent on the gate voltage V _ge according to the following equation [Math. 2]. The turn-off delay td of an element, for example a die 104, crossed by a current I _sw , can be calculated with the following equation [Math. 3] in function of the gate resistance R _g , the input capacitance Ci _es , the transconductance gfe, and the threshold voltage V _t h. [0028]

[Math. 1] [0029]

[Math. 2] [0030]

[Math. 3] [0031]

[Fig. 3], respectively [Fig. 4], represents an example of the evolution of the turn-off delay td, in function of the turn-off current I _tO fr (from which the current I _sw is here subtracted to have a reference to zero), respectively in function of the threshold voltage V*. The values shown on [Fig. 3] and [Fig. 4] are obtained for an element 11 which is, in the example, an IGBT known by its reference “CM100RX-24S1” and having the following nominal properties: V _cc = 15V ; V _ee = -5V ; R _g = 72 ; C _ies = 21 nF ; V _th = 6V and gfe = 43 A/V. [0032]

Therefore, the element(s) with higher current should start the turn-off current switching before than the (deteriorated) element with lower current. The turn-off of a degraded element crossed by a reduced current can be delayed of few nanoseconds to 100ns. Furthermore, the elements with a higher threshold voltage V _t h should start the turn-off current switching before than the (deteriorated) element with a lower threshold voltage V _t h. The turn-off of a degraded element submitted to a reduced voltage V* can be delayed of few nanoseconds to 40ns.

[0033]

The following [Table 1] is a summary of the effects of two types of degradation of an element 11 , wherein Ron is the resistance of the element 11 in the on-state, I _c is the current flowing through the element 11 , Tj is the junction temperature and V _ce is the steady-state voltage.

[0034]

[Table 1]

[0035]

[Fig. 5] shows the evolution of the current I _c flowing through two parallel elements 11.1 and 11.2 (here two IGBTs) of a module 1 at the turn-off commutation when the first element 11.1 is more degraded than the second element 11.2. As we can see, the turn-off of the degraded element 11.1 is delayed. It momentarily sees its current increasing since it is alone to hold a higher proportion of the total load current.

[0036]

A method for detection of a mismatch between parallel power electronic elements 11 into a power electronic module 1 can comprise: a. in response to the detection of a common turn-off of said elements 11, triggering a measuring period; b. during the measuring period, measuring a sequence of emitter voltages V ₆ E of at least one of said elements; c. extract data, from the measurements, said data including the sign and/or the amplitude of local extremums of said emitter voltage V _e E during the measuring period; d. deduce from the extracted data at least an existence or an absence of a mismatch between said elements.

[0037]

It is now referred to [Fig. 6] and [Fig. 7] as examples. [Fig. 6] corresponds to a configuration wherein two paralleled elements 11.1 and 11.2 (IGBTs) have a common gate driver, while [Fig. 7] corresponds to a configuration wherein two paralleled elements 11.1 and 11.2 (IGBTs) have each their own gate driver. The changes on the currents, respectively II and 12, flowing through an element, respectively 11.1 and 11.2, can be observed on corresponding voltages.

[0038]

On [Fig. 6] and [Fig. 7], the gate driver resistance and Kelvin resistors are not represented. Based on these examples, in various embodiments, each element 11 can comprise a single die or a combination of dies. The elements 11 of the same module 1 can be packaged together or not. They can have a common gate driver configuration ([Fig. 6]) or each their own corresponding gate driver ([Fig. 7]). The number of parallel power elements 11 in the module 1 is at least two. In various embodiments, it can be three, four, up to ten or even twenty for example.

[0039]

In the example of [Fig. 6] and [Fig. 7], the corresponding emitter voltage of the elements 11.1 and 11.2 are respectively V _e Ei and V _e E2, induced on the parasitic inductor, respectively L _e Ei and L _e E2, between an emitter pad on the power semiconductor element 11.1, respectively 11.2, to an external emitter pad of the module 1. Such an inductor L _e E is created by the connection of the power semiconductor element 11 to rest of the power module 1. The emitter pad on the power semiconductor element 11 can be measured using, for example, a Kelvin emitter disposed on the power module 1. In other words, the changes of the V _e Ei and V _e E2 (the shape of curves) are a proportional and derivative image of the power semiconductor currents because of the R-L behavior. As a skilled person in the art would understand, the corresponding voltages VeEi and V _e E2 can be measured at other points of the circuitry depending on the structure and the component types of each module 1: the above-described architecture with two IGBTs and parasitic inductors L _e Ei and L _e E2 are only examples, but the solution disclosed here is not limited to such architecture.

[0040]

In some embodiments, the turn-off event can be detected directly from the triggering signal sent by a controller of the module 1, or indirectly by detecting a first peak (an extremum) of an emitter voltage V ₆ E. TO detect a peak, the measured emitter voltage V _C E value can be compared to predetermined values. For example, a peak can be recognized if the emitter voltage V _C E value goes out of a nominal range centered on 0V, like -IV; IV, or -2V;2V.

[0041]

It is now referred to [Fig. 8]. The emitter voltages V _e Ei and V _e E2 of the elements 11.1 and 11.2 are measured (and stored) starting from an instant t corresponding to the common turn-off command signal of said elements 11.1 and 11.2. In other words, the measures are synchronized with the common turnoff triggering. The values shown on [Fig. 8] corresponds to the measures made on the structure shown on [Fig. 7] (two IGBTs with separate Gate driver configuration).

[0042]

<Mismatch or not mismatch> In some embodiments, if the aim is only to determine if there is, or not, a mismatch in the module 1 without needing to identify which element is the most degraded, to monitor the absolute value of a single emitter voltages V ₆ E of a single element 11 is sufficient, even if the sign is unknown, for example by comparing the said absolute value to a threshold value. The amplitude of local extremums of one emitter voltage V _e E during the measuring period enables to deduce an existence or an absence of a mismatch between the corresponding element 11 and another element 11 of the module 1. In some embodiments with the same aim (only to determine if there is, or not, a mismatch in the module 1 without needing to identify which element is the most degraded), to monitor the two signs of a pair of emitter voltages V _e Ei and V _e E2 of a pair of elements 11.1 and 11.2 is sufficient, even if the absolute value itself is unknown, for example by checking if the two signs are different. The signs of local extremums of two emitter voltages V _e Ei and V _e E2 during the measuring period enables to deduce an existence or an absence of a mismatch between the corresponding elements 11.1 and 11.2. These two possibilities (a single absolute value V _e E compared to a threshold value, or two signs of two values VeEi and V _e E2 compared one to the other) is the reason why we can say that the needed data are the signs “and/or” the amplitude of local extremums of emitter voltages of “at least one element”. Data comprising only one sign of a single value VeE should be avoided as it is less reliable to deduce the existence/ absence of a mismatch.

[0043]

<Most degraded, or not>

In some other embodiments, the aim is to determine if there is, or not, a mismatch in the module 1 , and, if there is a mismatch, to also determine if the element 11 of which the emitter voltage V _e E has been measured and extracted is or is not the most degraded, for example to plane a targeted intervention. The extremums (minimum and/or maximum) values of voltages V _e Ei and V _e E2 can be used to determine which element 11.1 or 11.2 conducts a large current as the switched current is inversely proportional to the minimum or the maximum value of the respective V _e Ei and V _e E2- In the example of [Fig. 8], Ic.u.i ⁼ 89A and Ic,n.2 = 107A. On [Fig. 9] and [Fig. 10], the measured values for a plurality of test cases are superimposed: zero, one, two, three, four and five wire lift-off situations in one element 11. Each curve corresponds to one of the situations. [Fig. 9] shows the measured emitter voltage V ₆ EI values of the element 11.1 while [Fig. 10] shows the measured emitter voltage V _e E2 values of the element 11.2. The following [Table 2] shows example of measured values (amplitude and sign) for amplitude (absolute value) above 0.5 V for both power elements 11.1 and 11.2 in the test case with five wire lift-offs.

[0044]

[Table 2]

[0045]

As an example, the first value going outside a predetermined rang (for example [-0.5V ; +0.5V]) is designated as the triggering “peak”, referenced “O” on the figures. The triggering peak can be used to define the temporal reference, trigger the measuring operation and synchronize them.

[0046]

In the example, the first peak “I” after the reference peak “O”, the extremum of emitter voltage V _C EI of the element 11.1 is positive (+3.65 V) while the extremum of emitter voltage V _e E2 of the element 11.2 is negative (-2.8V). Thus, it is possible to identify that element 11.1 is the most degraded among elements 11.1 and 11.2.

[0047]

If a single emitter voltage V ₆ E is measured and if it is possible to identify the first peak I corresponding to the turn-off triggering (for example in function of a command/triggering signal sent by a controller of the module 1), the sign of the emitter voltage V _e E of the first peak I is sufficient to identify if the corresponding element is the most degraded or not: if the sign is positive, it is the most degraded element. If the sign is negative, it is not the most degraded element. This is true even for modules comprising more than two paralleled elements. To identify the first peak I to consider implies to avoid any confusion with a preliminary peak resulting directly from the turn-off command signal (corresponding to the peak “O” on [Fig. 9] and [Fig. 10]. An example to identify distinctly the preliminary peak O and the first peak I is to directly monitor the triggering/command signal sent by a controller of the module 1.

[0048]

The values, and especially the signs, of the extremums are the key points of the measured values. To extract such data from the raw measurement signals can be made by using an Analog to Digital Converter (ADC). In some embodiment, the extraction of the extremums (identification of the “peaks”) from the measurements is made by an analogic and logical circuit, such that the use of a costly Analog to Digital Converter is made redundant.

[0049]

[Fig. 11] show examples of analogic and logical circuit that can be used. In the example described here, the analogic and logical circuit comprises a first signal conditioning circuit 201, a second signal conditioning circuit 202 and a module 203 including a RS flip flop and an inverter. In various embodiments, the analogic and logical circuit comprises other functionally equivalent portions.

[0050]

The waveform A is an emitter voltage V ₆ E measured on a most-degraded element 11. In practice, the status of relative degradation of each element 11 is unknown because it is one of the information that we want to determine. For example, if two power elements 11.1 and 11.2 are in parallel and 11.1 is more degraded, such a waveform is V _e Ei of the element 11.1 if the two emitters el and e2 of the power elements 11.1 and 11.2 are disconnected. When processed by the first signal conditioning circuit 201, respectively the second signal conditioning circuit 202, a logical signal Al, respectively A2, is outputted. When the pair of these two logical signals is analyzed, with the RS flip flop and an inverter (module 203), a logical signal is outputted (q=l ) meaning the power element 11.1 is the most degraded.

[0051]

The waveform B is an emitter voltage V _e E measured on a not-most degraded element 11. For example, if two power elements 11.1 and 11.2 are in parallel and 11.2 is not the most degraded, such a waveform is V _e 2ei = V _e E2-V _e Ei if the two emitters el and e2 of the power elements 11.1 and 11.2 are disconnected. When processed by the first signal conditioning circuit 201, respectively the second signal conditioning circuit 202, a logical signal Bl, respectively B2, is outputted. When the pair of these two signals is analyzed, with the RS flip flop and the inverter (module 203), a logical signal is outputted (q=0) meaning the power element 11.2 is not the most degraded.

[0052]

The waveform C is an emitter voltage V _e E measured on a not-most degraded element 11. For example, if two power elements 11.1 and 11.2 are in parallel and 11.2 is not the most degraded, such a waveform is V _e E2 of the element 11.2 if the two emitters el and e2 of the power elements 11.1 and 11.2 are disconnected.

[0053]

When processed by the first signal conditioning circuit 201, respectively the second signal conditioning circuit 202, a logical signal Cl, respectively C2, is outputted. When the pair of these two signals is analyzed, with a RS flip flop and an inverter (module 203), a logical signal is outputted (q=0) meaning the power element 11.2 is not the most degraded.

[0054]

To summarize, the output signal of the sequence analyzer 201, 202, 203 directly answers the logical question: “Is the monitored element the most degraded element?”.

[0055]

<Mismatch quantification>

In some embodiments, the degradation mismatch can be quantified. For example, assembly of a diode, a capacitor and a resistance, functioning as a peak detector, can be combined to the circuit shown on [Fig. 11]. A sampling by an ADC can be made, or the signal can be compared to a predetermined threshold value by a comparator, such that a quantification of the mismatch is obtained in function of the amplitude of extremum emitter voltage max(V _e E). [Fig. 12] is an example of such quantification to determine a number of wire lift-offs.

[0056]

<Kelvin to Kelvin voltage measurements>

In embodiments wherein a mismatch between only two elements 11 of a module 1 is monitored, a differential emitter voltage V _ee can be obtained (measured) on the emitter pads of the elements 11.1 and 11.2. In other embodiments, two measures can be compared: V _eie 2 = V _e Ei - V _e E2- Doing this, only one sensor and conditioning circuit is needed (one by pair of elements 11), and the sensitivity to degradation mismatch is increased. In addition, some dependency on temperature and on current are reduced. Such an implementation is compatible with both architecture: common or separate gate driver configurations (examples of [Fig. 6] and [Fig. 7]).

[0057]

[Fig. 13] shows the evolution of the emitter voltage V _eie 2 during a turnoff event, each curve corresponding to a specific number of wire lift-offs in the element 11.1, in a configuration of separated gate drivers. [Fig. 14] shows the evolution of the emitter voltage V _eie 2 during a turn-off event, each curve corresponding to a specific number of wire lift-offs in the element 11.1, in a configuration of common gate driver. [Fig. 15] shows the value of the negative extremum (minimum), a peak, in function of the degradation level unbalance quantified in number (n) of lift-offs, each curve corresponding to a specific situation of current I and temperature T, in a configuration of separated gate drivers. [Fig. 17] shows the same for positive extremum (maximum) of the emitter voltage V _eie 2- [Fig. 16] shows the same as [Fig. 15] in a configuration of common gate driver and [Fig. 18] shows the same as [Fig. 16] in a configuration of common gate driver.

[0058]

In view of [Fig. 13] to [Fig. 18], the amplitude of the peaks is function of the degradation level. This is the case for both the common and separate gate driver configurations. In embodiments wherein the extracted data includes the amplitudes of local extremums of the measured emitter voltages V ₆ E it is possible to deduce from the extracted data a quantification of a mismatch. When a sequence of emitter voltages V _e Ei and V _e E2 of a pair of elements 11.1 and 11.2 is measured by a Kelvin emitters sensor, it enables to obtain such information for modules 1 comprising such sensors.

[0059]

To use only one single Kelvin emitters sensor for a pair of elements 11 is possible for both configurations: connected elements (like in [Fig. 6]) and disconnected elements (like in [Fig. 7]). In addition, it is very convenient because a Kelvin emitters sensor is available in some existing architecture: it is unnecessary to modify such existing architectures to add a Kelvin emitters sensor. And such sensor is cheap with respect to other existing sensors.

[0060]

<Pair by pair monitoring>

In some embodiment, a multiplexer can be provided to connect a single monitoring circuit to the proper pair of elements 11 in order to advantageously limit the number of monitoring circuit to a single one even for a large number of power elements 11 in the module 1. The elements 11 are switched two by two, and for each pair, to monitor an emitter voltage V _eie 2.

[0061]

<Enhanced sensitivity>

In some embodiments, the method further comprises:

- imposing a supplementary external gate resistance during the measuring operation.

[0062]

By artificially increasing the gate resistance for the measurements, the mismatch sensitivity is increased during the single switching time and the resulting increased losses are limited in time (only during the small period of measurements). [Fig. 19] shows an example of a circuit that can be used to impose temporarily such an increased resistance. A switch M3 is opened only during the measurement thank to the inverted trigger signal. During the measurements, the total gate resistance is the sum of R _gex t and R _ge xt2- Otherwise, the module 1 operates in a normal mode only with the external gate resistance Rgext-

[0063]

<Feedback loop and Synchronization>

In some embodiments, the method is executed a first time to identify a most degraded element, and then, the method is reiterated at least one time with a retrofit loop arranged to induce a delay of the turn-off of at least one of the elements with respect to the other(s) such that to converge toward a temporarily synchronized first peaks I.

[0064]

Such embodiment with two elements 11.1 and 11.2 is represented on [Fig. 20]. The delay of the turn-off of the first element 11.1 is referenced ti and the delay of the turn-off of the second element 11.2 is referenced t2. In embodiments with more than two elements, the same method can be used by applying the same delay t to the turn-off of the elements that are not identified as the “most degraded”. The value of the induced delays ti and or t2 can be adjusted step by step until a temporal synchronization of the first peaks I is reached. Doing this, by reducing the temporal offset and even before to reach a perfect synchronization, the turn-off losses are at least partially balanced in the module 1 : the over-current in the module 1 is reduced and the resulting degradations consequences in the module 1 are reduced. The value of the absolute difference between the two imposed delays (|ti-t2|) can be used as an index of the relative degradation between the elements 11.1 and 11.2. For example, and as it is represented on [Fig. 20], value of the absolute difference between the two imposed delays (|ti-t2|) can be compared to a predetermined threshold value tth- An alert signal can be generated if the threshold value t* is exceeded.

[0065]

<Loop process>

In some embodiments, the method comprises a cyclically series of operations. In other words, the method described at the beginning is reiterated N times, for example in a period of several hours. And the measurements and/or extracted data are stored to constitutes a history of events related to the degradation of the elements 11 during an operational period of the module 1 longer than that of a single turn-off period. Then, or in real-time, the extracted data at the current time can be compared to the extracted data before. If the comparison shows that there is an evolution, a degradation index of the module 1 can be incremented. Once such a degradation index achieves a predetermined value (a threshold), a warning signal is generated.

[0066]

The degradation of the modules 1 can be observed during the entire lifetime even for the case where any mismatch is present on the V _e E waveforms. Furthermore, the current degradation level of each element 11 can be identified (not only related from one to another). The following [Table 3] shows an example of four measures made in an interval of 1000 hours each and the voltages of the first peaks I are measured and saved in the table.

[0067]

[Table 3]

[0068]

Data extracted and stored in [Table 3] shows that: - From Measure 2 compared to Measure 1 , the element 11.2 has been degraded faster than element 11.1 — > A degradation index of the element 11.2 can be increased

- From Measure 3 compared to Measure 2, the element 11.2 has been degraded faster than element 11.1 — A degradation index of the element 11.2 can be increased

- From Measure 4 compared to Measure 3, the element 11.1 has been degraded faster than element 11.2 A degradation index of the element 11.1 can be increased.

[0069]

In the example described here, the threshold value to trigger an alert/waming signal is previously set to correspond to a situation wherein fifth wire bonding are lift-off. The threshold value is obtained by testing prototypes. The definition of the threshold value can vary and can be adapted to the context by a person skilled in the art.

[0070]

[Fig. 21] shows a schematic example of the evolution over the time of the voltage V _eie 2 between the two emitters of elements 11.1 and 11.2, and the corresponding degradation indexes.

[0071]

<Conclusion>

The differential electrical, thermal and degradation of parallel power elements leads to current unbalance in steady state. This is due to the non- homogeneous electrical resistance, junction temperature creating a non- homogeneous current distribution. Monitoring this current unbalance is thus a differential electrical, thermal and damage sensitive parameter. However, it requires monitoring the individual power element currents at relatively high resolution which is technically complex and costly. [0072]

The methods based on monitoring the transient switching waveforms were generally considered expensive, inaccurate and non-robust due to the high frequency sensor requirements, the low sensitivity and the complex dependencies with operating conditions and design.

[0073]

In order to achieve high current capabilities, a technique consists to parallel power elements (dies, converters or sub-set of elements for example). This solution is largely adopted given the flexibility and scalability of the current power electronics installations. Among the problematic that should be faced with the parallelisation of the power electronics installations, the current distribution caused by the nonuniform electrical-thermal-damage characteristics should be identified during the commissioning, usage and maintenance phases.

[0074]

A problem addressed by the method above disclosed is the safe, accurate, and low-cost current distribution and degradation monitoring of the electro-thermal interconnections of individual power elements in parallel, and automatic generation of alert signals. By (at least) identifying the mismatches based on the sign and/or the amplitude of a sequence of peaks during the turnoff switching time using the V _e E (voltage between kelvin and emitter) of the power elements, it is possible to address such a problem.

[0075] industrial Applicability>

The technical solutions presented here can be used to automatically trigger alert signals to implement corrective actions, such as repairs or functional adaptations to the power modules, or even targeted replacements. [0076]

This disclosure is not limited to the methods, modules and computer programs described here, which are only examples. The invention encompasses every alternative that a person skilled in the art would envisage when reading this text.

[0077]

<Reference Signs List>

- 1 : System

- 11: power electronic element

- 2: conductive wire bond

- 101: electrical insulator layer

- 102: conductive layer

- 103: solder layer

- 104: semiconductor die

- 105: metallization layer

- 201: signal conditioning circuit

- 202: signal conditioning circuit

- 203: RS flip flop and inverter

- O: triggering peak

- 1: first peak

- II: second peak

-III: third peak

- A: waveform

- B: waveform

- C: waveform.