FIELD OF THE INVENTION

The present invention relates to the field of current and/or voltage measurement in an industrial automation and control system, in particular in a substation or power grid automation system. In particular, the present invention relates to a device and a method for current and/or voltage measurement in such a system.

BACKGROUND OF THE INVENTION

Measurement of electrical signals such as current and/or voltage is an important task in an industrial automation and control system, in particular in a substation or power grid automation system. Often in substation or power grid automation systems, the secondary current or voltage of a primary instrument transformer is measured by a device such as an Intelligent Electronic Device, IED, e.g., a digital relay, a merging unit, a process level device, or a phasor measurement unit. The measured signals are used for control, metering, as well as protection applications. Hence, the measurand can range from a fraction of a nominal current or voltage level to fault currents and fault voltages at high multiples of the nominal level. Accordingly, the measurement devices require a high dynamic range. This is achieved in prior art by several hardware paths in the device adapted for different measurand ranges. Obviously, this requires more hardware components and adds to the cost of the device.

DESCRIPTION OF THE INVENTION

It is an objective of the present invention to provide a device and a method for current and/or voltage measurement in an industrial automation and control system, in particular in a substation or power grid automation system, with a high dynamic range in a single input channel. An input channel comprises an input circuit, which mainly comprises analog electronic components, an Analog-to-Digital Converter, ADC, and a digital part. In a number of applications in substation and power grid automation to improve the measurement quality as well as the device and operator safety, the input circuit and an analog end of the ADC may be galvanically isolated from the digital part of the input channel. ADCs available with galvanic separation may not be available with sufficiently high bit rates or dynamic range to cover the required measurand range in a single input channel, i.e., the may have in itself a low dynamic range, increasing the need of the present invention for these applications. Furthermore, solutions employing different input channels for different measurand ranges become even more expensive when galvanic isolation is required. In addition, the method and the device have to comply with requirements for protection applications wherein nearly instantaneous overcurrent signals and waveform artefacts have to be measured. Furthermore, the present invention can be carried out with relatively inexpensive electronic components as an ADC with a low dynamic range and, in addition to ADC and a digital signal processor or the like, with simple discrete components such as switches and resistors, in particular, it can be carried without any integrated adjustable gain amplifier.

These objectives are achieved by the subject-matter of the independent claims. Further exemplary embodiments are evident from the dependent claims and the following description.

A first aspect of the present invention relates to a device for current and/or voltage measurement in an industrial control and automation system, in particular a substation or power grid automation system. This device comprises an input circuit, configured to receive an electrical input signal, in particular an analog electrical signal, to scale the electrical input signal by a scaling factor, to receive a scaling signal, and to set the scaling factor according to the scaling signal to at least a first or a second value. The device further comprises an ADC, in particular a delta-sigma ADC, having an analog end, the analog end being electrically connected to the input circuit, and a digital end; the ADC is configured to convert the scaled electrical input signal into an intermediate digital signal and to output the intermediate digital signal at the digital end. The device further comprises a first signal path, e.g., a feedback loop, wherein the first signal path is connected to the digital end of the ADC and is configured to create the scaling signal and to send the scaling signal to the input circuit. Herein, the device is configured to set, based, in particular based only, on the intermediate digital signal of a sample period or of a clock cycle and the scaling factor of the sample period or of the clock cycle, in particular during the sample period or clock cycle, the scaling factor for a subsequent sample period or for a subsequent clock cycle. Herein, the sample period or the clock cycle may be the sample period or the clock cycle of the first signal path; the subsequent sample period or clock cycle may be the subsequent sample period or clock cycle of the first signal path.

The device may further comprise a second signal path that is connected to the digital end of the ADC and is configured to create a refined digital signal from the intermediate digital signal using the scaling factor, wherein the second signal path has a second sampling rate, e.g., 1 kS/s to 200 kS/s, in particular 20 kS/s and the first signal path has a first sampling rate higher than the second sampling rate, in particular by at least a factor of 2, 5, or 10, e.g., lOkS/s to 2000kS/s, in particular 500kS/s. The second signal path may be further configured to output the refined digital signal for further processing such as for outputting to a user interface, for creation of time-critical messages and/or sampled value messages, for creation of phasor data, for revenue metering, and/or as input of protection functions. The first signal path may be further configured to send the scaling signal or an indication of the scaling factor to the second signal path. The second signal may further be configured to receive the scaling signal or the indication of the scaling signal.

In embodiments, the first signal path may be further configured to create an auxiliary digital signal from the intermediate digital signal, in particular using the scaling factor. This may be achieved, e.g., by division of the intermediate digital signal by the scaling factor, and possible further multiplication with correction factors and/or application of one or more filters, and in particular without using a temporal change and/or a slew rate of the intermediate digital signal; e.g., the auxiliary digital signal may not be a predicted or forecasted value for the electrical input signal for a subsequent sample period. The device may be configured to set the scaling factor for the subsequent sample period by comparing the auxiliary digital signal of the sample period with at least one threshold. In embodiments, the at least one threshold may depend on the scaling factor of the sample period.

The ADC, the first signal path, the second signal path, and/or the device may be configured to operate in a clocked manner.

By way of example, the scaling factor may have at least a first value or a second value with the second value being larger than the first value. In this case, the device may be configured to conduct the comparison of the auxiliary digital signal of the sample period with at least one threshold as follows: when the scaling factor of the sample period has the second value and the auxiliary digital signal of the sample period is positive and above a first threshold, the device is configured to set the scaling factor for the subsequent sample period to the first value; when the scaling factor of the sample period has the first value and the auxiliary digital signal of the sample period is positive and below a second threshold, the device is configured to set the scaling factor for the subsequent sample period to the second value; when the scaling factor of the sample period has the second value and the auxiliary digital signal of the sample period is negative and below a third threshold, the device is configured to set the scaling factor for the subsequent sample period to the first value; when the scaling factor of the sample period has the first value and the auxiliary digital signal of the sample period is negative and above a fourth threshold, the device is configured to set the scaling factor for the subsequent sample period to the second value. In this example, first and second threshold, on the one hand, as well as third and fourth threshold, on the other hand, may coincide or be different, in particular by at least 1% or 5% of the first or the third threshold. E.g, the absolute value of the first and third threshold may be larger than the absolute value of the second and the fourth threshold, respectively. This introduces a feedback loop with hysteresis that increases the stability of the measurement.

In embodiments, the input circuit and the analog end of the ADC are galvanically isolated from the digital end of the ADC, the first signal path, and the second signal path, in particular wherein the ADC is an isolated ADC and the first signal path is separated from the input circuit, e.g., by isolation transformers and/or opto-isolators; the input circuit and/or the analog end of the ADC may use a voltage supply different from the voltage of the digital end of the ADC, the first signal path and/or the second signal path.

The input circuit may comprise one or more resistors and a switch, in particular as a discrete component, the switch being controllable by the scaling signal, wherein the switch may have at least a first state and a second state; the input circuit may be further configured to scale the electrical input signal at least in one of the first and the second state of the switch by a voltage drop across a subset of the one or more resistors; and the scaling factor may have the first value with the switch in the first state and the second value with the switch in the second state, in particular, wherein in the switch is arranged in the input circuit to connect/disconnect and/or shorten at least one of the one or more resistors in the input circuit. In this case, the analog end of the ADC may comprise a first terminal and a second terminal, the input circuit may comprise a first line, connected to the first terminal, and a second line, connected to the second terminal, wherein a series of the switch and the subset of the one or more resistors is connected with the first line and the second line.

In further embodiments, the input circuit and/or the device may be devoid of any amplifier and/or programmable/variable gain amplifier, in particular as a discrete component.

Furthermore, the second signal path may comprise one or more filters adapted to increase the resolution of the refined digital signal.

In embodiments, the scaling factor may not be larger than 1, i.e., it may be 1 or smaller. In other words, the input circuit is configured to attenuate the electrical signal and/or not to amplify the electrical signal.

The device may be a module for analog-to-digital conversion in an intelligent electronic device, in an intelligent electronic device in a substation or power grid automation system, in a process level device, in a merging unit, in a digital relay, or in a phasor measurement unit.

A second aspect of the present invention relates to an intelligent electronic device, an intelligent electronic device in a substation or power grid automation system, a process level device, a merging unit, a digital relay, or a phasor measurement unit comprising a device according to the first aspect of the invention.

A third aspect of the present invention relates to a method for current and/or voltage measurement in an industrial control and automation system, in particular a substation or a power grid automation system. The method can be executed using a device of the first aspect and/or the second aspect of the present invention. The method comprises

receiving an, in particular analog, electrical input signal, in particular by an input circuit;

scaling, in particular in the input circuit, the electrical input signal by a scaling factor having at least a first value or a second value;

converting the scaled electrical input signal into an intermediate digital signal, in particular by an Analog-to-Digital Converter, ADC;

creating an auxiliary digital signal from the intermediate digital signal, in particular using the scaling factor, in particular via a first signal path; setting the scaling factor, in particular for a subsequent clock cycle or sample period, based at least on the auxiliary digital signal, in particular of the sample period or the present sample period.

Herein, the auxiliary digital signal may be created without using a temporal change and/or a slew rate of the intermediate digital signal; e.g., the auxiliary digital signal may not be a predicted or forecasted value for the electrical input signal for a subsequent sample period.

The method may further comprise creating a refined digital signal from the intermediate digital signal using the scaling factor, in particular by a second signal path, wherein creating the auxiliary digital signal is executed faster than creating the refined digital signal, in particular by at least a factor of 2, 5, or 10.

In embodiments, setting the scaling factor may be based on the auxiliary digital signal and on a current value of the scaling factor.

These and other aspects of the present invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject-matter of the present invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings.

Fig. 1 schematically depicts an embodiment of the first aspect of the present invention.

Fig. 2 schematically depicts a further embodiment of the first aspect of the present invention.

Fig. 3 schematically depicts a further embodiment of the first aspect of the present invention.

Fig. 4 schematically depicts a further embodiment of the first aspect of the present invention.

Fig. 5 schematically depicts examples of scaling signal, intermediate digital signal, and refined digital signal as a function of time.

Fig. 6 schematically depicts further examples of scaling signal, intermediate digital signal, and refined digital signal as a function of time. Fig. 7 schematically depicts an example of the auxiliary digital signal as a function of time with first, second, third, and fourth threshold.

The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present invention will be described in more detail with reference to the drawings, in which exemplary embodiments are shown.

In Fig. 1, an embodiment of a device according to a first aspect of the present invention is schematically depicted. Here, an input circuit comprises lines and terminals to receive an electrical input signal 100, an attenuator/amplifier 235 adapted to scale the electrical input signal 100 by a scaling factor, and further lines connecting the input circuit to an analog end of an ADC 220 and adapted to guide a scaled electrical input signal 103 to the ADC 220. The electrical input signal can be AC or DC and can be e.g. an electrical input current or an electrical input voltage. In case of an electrical input current, a shunt may be used to convert the current into voltage. The attenuator/amplifier 235 can be any type of electrical or electronic component that is adapted to scale an input electrical signal by a scaling factor and is further adapted to receive a scaling signal to set the scaling factor according to the scaling signal, i.e. is controllable by the scaling signal; the scaling factor can have at least a first and a second value. By way of example, the attenuator/amplifier 235 can be a variable gain amplifier, an assembly comprising one or more element of the group consisting of a switch, a resistor, a gain amplifier, and a transistor. In embodiments, the input circuit and/or the attenuator/amplifier 235 can also be devoid of any amplifier, in particular, any programmable/variable gain amplifier. The ADC 220 converts the scaled electrical signal 103 into an intermediate digital signal 120 that is output at a digital end of the ADC 220. The ADC 220 may be a delta-sigma ADC or any other kind of ADC. A first signal path 211 is connected to the digital end of the ADC 220 to receive the intermediate digital signal 120. In the first signal path 211, an auxiliary digital signal may be created from the intermediate digital signal 120, e.g. by dividing the auxiliary digital signal by the scaling factor, by application of one or more filters, for example to increase the resolution of the auxiliary digital signal, and/or by multiplication with correction, conversion, and/or normalization factors. Hence, the auxiliary digital signal may represent or may be proportional to an estimate of the electrical input signal 100. Based on the auxiliary digital signal of a sample period or clock cycle, e.g., a current sample period or current clock cycle, a scaling signal 110 is created to set the scaling factor for a subsequent sample period or clock cycle. To this end, the scaling signal 110 may be delayed or synchronized. For setting the scaling factor, the auxiliary digital signal may be compared with one or more thresholds. E.g., in case the auxiliary digital signal of the sample period is above a threshold; the scaling factor for the subsequent sample period may be set to a lower value, e.g., to the first value being lower than the second value. In embodiments, the one or more threshold and/or the criteria for comparison may depend on the scaling factor of the sample period or clock cycle. E.g., as an alternative to division of the auxiliary digital signal by the scaling factor, the at least one threshold may be multiplied with the scaling factor. The scaling signal may be sent to the input circuit in any case or only in case of change of the scaling factor. In other words, the first signal path 211 is a feedback loop for the scaling, attenuation, and/or gain of the electrical input signal 100 in the input circuit or the attenuator/amplifier 235. With the at least one threshold depending on the scaling factor of the sample period, a hysteresis in the feedback loop can be achieved that stabilizes the feedback loop as shown further below. Since the auxiliary digital signal does not require a high resolution, i.e., only at maximum a few or even no filters have to be applied to the auxiliary digital signal, and the auxiliary digital signal is not used to calculate a forecasted or a predicted value of the electrical input signal or a slew rate of the electrical input signal 100, the scaling signal 110 can be sent very fast to the input circuit or the attenuator/amplifier 235. In other words, the scaling signal 110 and/or the auxiliary digital signal can be created at a very high sampling rate, e.g., the sampling rate of the first signal path 211, i.e., the first sampling rate, can be between lOkS/s lOOkS/s to 2000kS/s, in particular 500kS/s.

The intermediate digital signal 120 may be used for further processing such as for outputting to a user interface, for creation of time-critical messages and/or sampled value messages, for creation of phasor data, for revenue metering, and/or as input of protection functions. To this end, a refined digital signal 140 may be created from the intermediate digital signal 120 and the scaling factor, e.g., in a second signal path 212 that is connected to the digital end of the ADC 220. Hence, the first signal path 211 may be configured to send the scaling signal 110 or an indication of the scaling factor to the second signal path 212; the second signal path 212 may be configured to receive the scaling signal 110 or the indication of the scaling factor. The refined digital signal 140 may require a higher resolution than the auxiliary digital signal; but may be processed at a lower sampling rate. A typical sampling rate of the second signal path is 1 kS/s to 90kS/S or 200 kS/s, in particular 20 kS/s; i.e., the first signal path 211 has a sampling rate, i.e., a second sample rate, higher than the sampling rate of the second signal path 212, in particular, by at least a factor of 2 or 10. The first signal path and/or the second signal path can at least partially be realized in a microcontroller, a DSP, a FPGA, and/or an ASIC. The ADC 220, the first signal path 211, and/or the second signal path 212 may be operated in a clocked manner; to this end, they may receive a clock signal; ADC 220, the first signal path 211, and/or the second signal path 212 can be commonly be connected to one clock or be connected to different clocks; i.e., they may have common sample periods or different sample periods.

Fig. 2 schematically depicts a further embodiment according to the first aspect of the present invention. The input circuit comprises a resistor R5 and a switch 230 that has a first state, i.e., a closed state, and a second state, i.e., an open state, and is controllable by the scaling signal 110. The scaled electrical input signal 103 is scaled by a scaling factor of 1 with the switch 230 in the closed state and is scaled by a scaling factor RADC/(R5+RADC) in the open state with RADC being the input resistance of the ADC 220. The device furthermore comprises a clock 213 which is connected to the ADC 220, first signal path 211, and second signal path 212 and sends a clock signal 180 to them.

Fig. 3 schematically depicts a further embodiment according to the first aspect of the present invention. The input circuit comprises a number of resistors Rl, R2, R3, R4 and a number of ground GND contacts. The switch 230 has has a first state, i.e., the open state, and a second state, i.e., the closed state, and is controllable by the scaling signal 110. In the open state, the scaled electrical input signal 103 is scaled by a scaling factor of R2/(R1+R2) while in the closed state the scaled electrical input signal 103 is scaled by a scaling factor of R2| I R3/(R1+ R2| I R3) with R2| I R3=1/(R2 ¹ +R3 ¹ ). In this embodiment, first signal path 211 and second signal path 212 are realized in a microcontroller 210. The microcontroller 210 comprises a clock 213 that sends a clock signal 180 to the first signal path 211 and the second signal path 212 as well as to the ADC 220. In this embodiment, there is a galvanic isolation, indicated by the isolation barrier 200, between the input circuit, the analog end of the ADC, on the one hand, as well as the first signal path 211, the second signal path 212, and the digital end of the ADC 220. To this end, the embodiment comprises an isolated switch buffer 240, which buffers the scaling signal 110, and an isolated power supply 252. The embodiment furthermore comprises a power supply 251 that provides a supply voltage 170 to a portion of the ADC 220, the microcontroller 210, a portion of the switch buffer 240, and an isolated power supply 252. The isolated power supply 252 provides a supply voltage 170 to a further portion of the switch buffer 240, the switch 230, and a further portion of the ADC 220. The isolation barrier 200 can be achieved by isolation transformers and/or opto-isolators in the isolated power supply 252, the ADC 220, and the switch buffer 240.

Fig. 4 schematically depicts a further embodiment according to the first aspect of the present invention similar to the previously described embodiment. However, the electrical input signal is an electrical input current 102. Hence, the input circuit comprises a shunt RS that converts the current into a voltage; the electrical input signal is then scaled by scaling factor of R2/(R1+R2) in the open state of the switch 230 and by a scaling factor of R2| I R3/(R1+ R2| I R3) in the closed state of the switch 230. The resistance of the shunt RS can be applied as a correction factor to the auxiliary digital signal and the refined digital signal to calculate a current signal from the measured voltage.

Regarding all embodiments disclosed above, resistors Rl, R2, R3, R4, and/or R5 as well as shunt RS and/or the ADC input resistance RADC may be ohmic resistors.

Fig. 5 depicts by way of example, the scaling signal 110, the intermediate digital signal 120, and the refined digital signal 140 as a function of time; the time axis 150 of the graph is given in seconds, while the signal axis 160 is in arbitrary units. The feedback loop given by the first signal path has a hysteresis which results in asymmetric switching behaviour of the scaling factor for falling and rising input signals. This way, a stable switching behaviour can be achieved, even in the presence of electrical noise in the device.

In contrast, Fig. 6 depicts by way of example, the scaling signal 110, the intermediate digital signal 120 and the refined digital signal 140 as a function of time, wherein the feedback loop given by the first signal path has no hysteresis. Here, the switching behaviour is not stable in the vicinity of the thresholds due to electrical noise in the device.

For further illustration, Fig. 7 depicts by way of example, the electrical input signal 130 as a function of time with the dashed lines indicating a first threshold 310, a second threshold 320, a third threshold 330, and a fourth threshold 340 wherein the absolute value of the first threshold 310 is larger than the absolute value of the second threshold 320 and the absolute value of the third threshold 330 is larger than the absolute value of the fourth threshold 340. In this example, the scaling factor may have at least a first value or a second value with the second value being larger than the first value and the device may be configured to conduct the comparison of the auxiliary digital signal of the sample period with at least one threshold 310, 320, 330, 340 as follows: when the scaling factor of the sample period has the second value and the auxiliary digital signal 130 of the sample period is positive and above the first threshold 310, the device is configured to set the scaling factor for the subsequent sample period to the first value; when the scaling factor of the sample period has the first value and the auxiliary digital signal 130 of the sample period is positive and below a second threshold 320, the device is configured to set the scaling factor for the subsequent sample period to the second value; when the scaling factor of the sample period has the second value and the auxiliary digital signal 130 of the sample period is negative and below a third threshold 330, the device is configured to set the scaling factor for the subsequent sample period to the first value; when the scaling factor of the sample period has the first value and the auxiliary digital signal 130 of the sample period is negative and above a fourth threshold 340, the device is configured to set the scaling factor for the subsequent sample period to the second value. In this example, first 310 and second threshold 320, on the one hand, as well as third 330 and fourth threshold 340, on the other hand, are different, in particular by at least 1% or 5% of the first or the third threshold, respectively. This way, zones of no switching of the scaling factor are formed for signals between first 310 and second threshold 320 as well as between third 330 and fourth threshold 340, introducing a hysteresis feedback that prevents instable switching behaviour as illustrated in Fig. 6.

While the invention has been described in detail in the drawings and foregoing description, such description is to be considered illustrative or exemplary and not restrictive. Variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word“comprising” does not exclude other elements or steps, and the indefinite article“a” or“an” does not exclude a plurality. The mere fact that certain elements or steps are recited in distinct claims does not indicate that a combination of these elements or steps cannot be used to advantage, specifically, in addition to the actual claim dependency, any further meaningful claim combination shall be considered disclosed. LIST OF REFERENCE SYMBOLS

100 electrical input signal

101 electrical input voltage

102 electrical input current

103 scaled electrical input signal

Rl, R2, R3, R4, R5 resistors

GND ground

110 scaling signal

120 intermediate digital signal 130 auxiliary digital signal 140 refined digital signal 150 time axis in seconds 160 signal axis in arbitrary units 170 supply voltage

180 clock signal

200 isolation barrier

210 microcontroller

211 first signal path

212 second signal path

213 clock

220 ADC

230 switch

RS shunt

235 attenuator/ amplifier 240 switch buffers

251 power supply

252 isolated power supply 310 first threshold

320 second threshold

330 third threshold

340 fourth threshold