Title:
METHOD FOR DRIVING A NONVOLATILE LOGIC CIRCUIT AS AN EXCLUSIVE-OR CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/111305
Kind Code:
A1
Abstract:
In contact with a semiconductor film (14), the disclosed nonvolatile logic circuit has a power-supply electrode (15), an output electrode (16), and in the region therebetween, a 2×2 matrix of input electrodes (17). The disclosed nonvolatile logic circuit also has a control electrode (11) formed on a principal surface of the semiconductor with a ferroelectric film (13) interposed therebetween. Signals applied to the four input electrodes consist of a first input signal, a second input signal, the logical negation of the first signal, and the logical negation of the second signal. For either pair of electrodes adjacent along the axis connecting the power-supply electrode and the output electrode, the signals inputted thereto are, respectively, one of the input signals and the logical negation of the other input signal. For either pair of electrodes diagonally adjacent, the signals inputted thereto are, respectively, one of the input signals and the logical negation of that same input signal.
Inventors:
KANEKO, Yukihiro (())
Application Number:
JP2011/000801
Publication Date:
September 15, 2011
Filing Date:
February 14, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
International Classes:
H03K19/21; G11C11/22; H01L21/8246; H01L27/105; H01L29/786
Attorney, Agent or Firm:
OKUDA, Seiji (OKUDA & ASSOCIATES, 10th Floor Osaka Securities Exchange Bldg., 8-16, Kitahama 1-chome, Chuo-ku, Osaka-sh, Osaka 41, 〒5410041, JP)
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