MAGNETIC RANDOM ACCESS MEMORY (TEF-RAM) DEVICE AND TEF-

RAM DEVICE

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore Patent Application No. 10201508022T, filed 28 September 2015, the content of which being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] The present invention generally relates to a method of error detection in a toggle electric field magnetic random access memory (TEF-RAM) device and a TEF- RAM device/system including an error detection module.

BACKGROUND

[0003] Spin transfer torque magnetic random access memory (STT-MRAM) device has attracted enormous attention and effort from various research and industry parties due to its prominent features such as lower switching current, high thermal stability, better scalability, and so on. The effort to discover new switching phenomenon that further reduces power consumption, improves switching speed, and so on, continues to drive the technology forward.

[0004] Recently, a new type of memory cell, namely, toggle electric field magnetic random access memory (TEF-RAM) cell, that makes use of synthetic antiferromagnetic free layer to achieve very fast switching at very low power consumption was disclosed in Tran et al. (Singapore patent application no. 10201400395Q, which US patent application no. 14/632,442 (US publication no. US 2015/0255135 Al) claims priority to), the contents of both being hereby incorporated by reference in their entirety for all purposes. The switching of the TEF-RAM cell exhibits toggling characteristic in response to applied short voltage pulses. [0005] A single mode memory device/system based on TEF-RAM cells has been disclosed in Foong et al. (Singapore patent application no. 10201500289W, which International application no. PCT/SG2015/050520 (International publication no. WO 2016/114718 Al) claims priority to), the contents of both being hereby incorporated by reference in their entirely for all purposes. For the single mode TEF-RAM device, read- before-write programming scheme is employed for the programming the memory cells due to the toggling switching behavior of the memory cells, and a mid-point reference sensing scheme is adopted for reading the memory cells. However, such an approach in reading the memory cells may lead to high capacitive mismatch at the two input terminals of the sense amplifier of the TEF-RAM device, compromising the limited sensing margin. In addition, the mid-point reference unit for providing a reference voltage to the sense amplifier for reading the memory cells may include four TEF-RAM cells and a number of pass transistors or control switches, and such components may have reliability and accuracy issues. For example, when one or more of the TEF-RAM cells in the mid- point reference unit fails, the resulting reference voltage generated by the mid-point reference unit for use by the sense amplifier as a comparison to read the memory cells may become inaccurate and the reading output data may thus be incorrect.

[0006] A differential STT-MRAM cell was disclosed in Ong (US patent no. 8,077,501 B2), whereby a one-bit information is stored in a complementary manner in the differential STT-MRAM cell including a pair of STT-MRAM elements (magnetic tunnel junctions (MTJs)) that are disposed so as to store and supply differential data therein. In operation, a write driver delivers a pair of complementary voltages to the bit lines and source lines of the two STT-MRAM elements to program one of them in an anti-parallel (AP) state (i.e., the electron spin directions in the free and reference layers in the MTJ are in an AP state) and the other in a parallel (P) state (i.e., the electron spin directions in the free and reference layers in the MTJ are in a P state). To read the STT-MRAM cell, the sense amplifier directly compares the current output from the two STT-MRAM elements of the STT-MRAM cell. Therefore, a faster and more reliable read operation may be achieved due to the doubled sense margin and matched capacitive and resistive load at the two inputs of the sense amplifier. However, differential STT-MRAM cells may suffer from soft errors whereby the two STT-MRAM elements are in the same AP or P resistance states due to write error or read disturbance. Soft error correction techniques for differential STT-MRAM were disclosed by Noguchi et al. ("Highly reliable and lower-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU", Symposia on VLSI Technology and Circuits, June 2014, pp. 120-121), which involve an extra sensing step with mid-point or fixed reference. However, such techniques do not apply to differential mode TEF-RAM. Besides, hard error cell (e.g., involving open, short, and unswitchable memory cells) detection for differential memory system using circuit technique has not been disclosed.

[0007] A need therefore exists to provide a method of error detection in a TEF-RAM device, and a TEF-RAM device including an error detection module. For example, on- chip error detection before product testing and shipping as well as on the field of operation is advantageous to maximize yield and ensure correct functionality for memories of various technologies and architectures. It is against this background that the present invention has been developed.

SUMMARY

[0008] According to a first aspect of the present invention, there is provided a method of error detection in a toggle electric field magnetic random access memory (TEF-RAM) device, the method comprising:

performing a first read operation on a memory cell of the TEF-RAM device to obtain a first read output of the memory cell;

performing a first write operation on the memory cell after the first read operation;

performing a second read operation on the memory cell after the first write operation to obtain a second read output of the memory cell; and

determining whether an error exists with the memory cell based on the first read output and the second read output.

[0009] In various embodiments, the error comprises a first type of error, and said determining whether an error exists with the memory cell comprises determining whether the first type of error exists with the memory cell based on whether the first read output and the second read output are the same or different. [0010] In various embodiments, said determining whether the first type of error exists with the memory cell comprises:

determining that the first type of error exists with the memory cell when the first read output and the second read output obtained are the same; and

determining that the first type of error does not exist with the memory cell when the first read output and the second read output obtained are different.

[0011] In various embodiments, the first read output and the second read output are the same when both are at a first state, or both are at a second state, and the first read output and the second read output are different when the first read output is at the first state and the second read output is at the second state, or vice versa.

[0012] In various embodiments, the TEF-RAM device is a single mode TEF-RAM device.

[0013] In various embodiments, said performing a first read operation comprises performing at least two read operations on the memory cell to obtain at least two read outputs of the memory cell, wherein a first of the at least two read operations is performed to obtain a first of the at least two read outputs of the memory cell, and a second of the at least two read operations is performed based on the first of the at least two read outputs to obtain a second of the at least two read outputs of the memory cell, the second of the at least two read outputs corresponding to said first read output of the memory cell.

[0014] In various embodiments, the second of the at least two read operations is selected from one of a read operation with a negative bias and a read operation with a positive bias based on the first of the at least two read outputs of the memory cell.

[0015] In various embodiments, the second of the at least two read operations is selected to be the read operation with a negative bias when the first of the at least two read outputs of the memory cell obtained is at a first state, and the second of the at least two read operations is selected to be the read operation with a positive bias when the first of the at least two read outputs of the memory cell obtained is at a second state.

[0016] In various embodiments, the error comprises at least one of a first type of error and a second type of error, and said determining whether an error exists with the memory cell comprises determining whether the first type of error or the second type of error exists with the memory cell based on whether the at least two read outputs and the second read output of the memory cell are the same or different.

[0017] In various embodiments, said determining whether the first type of error or the second type of error exists with the memory cell comprises determining that the first type of error exists with the memory cell when the at least two read outputs and the second read outputs of the memory cell obtained are the same.

[0018] In various embodiments, said determining whether the first type of error or the second type of error exists with the memory cell comprises determining that neither the first type of error nor the second type of error exist with the memory cell when the at least two read outputs of the memory cell obtained are the same and the second read output of the memory cell is different to the at least two read outputs.

[0019] In various embodiments, the TEF-RAM device is a differential mode TEF- RAM device, and the memory cell comprises a first memory element and a second memory element differentially coupled together for storing differential data.

[0020] In various embodiments, when the at least two read outputs are different, said performing a first write operation comprises performing the first write operation only on one of the first and second memory elements, and the method further comprises performing a third read operation on the memory cell after the second read operation to obtain a third read output of the memory cell.

[0021] In various embodiments, the method further comprises performing a fourth read operation on the memory cell after the third read operation to obtain a fourth read output of the memory cell, wherein said determining whether the first type of error or the second type of error exists with the memory cell is further based on at least one of the third and fourth read outputs.

[0022] In various embodiments, when the at least two read outputs obtained are different:

said performing a first write operation comprises performing the first write operation only on the first memory element;

the second read operation is the read operation with a positive bias; and the method further comprises: performing a second write operation on both the first and the second memory elements before the third read operation is performed when the second read output obtained is at the second state, and

performing a third write operation on both the first and the second memory elements before the fourth read operation is performed when the third read output obtained is at the first state,

wherein said determining whether the first type of error or the second type of error exists with the memory cell comprises:

determining that the first type of error exists with the memory cell when the third read output obtained is at the second state or when the fourth read output obtained is at the first state; and

determining that the second type of error exists with the memory cell when the fourth read output obtained is at the second state.

[0023] In various embodiments, when the at least two read outputs obtained are different: said performing a first write operation comprises performing the first write operation only on the second memory element;

the second read operation is the read operation with a negative bias; and the method further comprises:

performing a second write operation on both the first and the second memory elements before the third read operation is performed when the second read output obtained is at the first state, and

performing a third write operation on both the first and the second memory elements before the fourth read operation is performed when the third read output obtained is at the second state,

wherein said determining whether the first type of error or the second type of error exists with the memory cell comprises:

determining that the first type of error exists with the memory cell when the third read output obtained is at the first state or when the fourth read output obtained is at the second state; and determining the second type of error exists with the memory cell when the fourth read output obtained is at the first state.

[0024] In various embodiments, the first type of error is a hard error of the memory cell whereby a resistance state of the memory cell is unswitchable by a write operation configured for switching the resistance state of the memory cell, and the second type of error is a soft error whereby the first and second memory elements of the memory cell are at the same resistance state.

[0025] In various embodiments, the first state is a high state or a binary logic 1 state, and the second state is a low state or a binary logic 0 state.

[0026] According to a second aspect of the present invention, there is provided an error detection module for a toggle electric field magnetic random access memory (TEF- RAM) device, the error detection module configured to control a read circuit and a write circuit of the TEF-RAM device to perform the method of error detection in the TEF- RAM device according to the first aspect of the present invention to determine whether an error exists with one or more of a plurality of memory cells in the TEF-RAM device.

[0027] According to a third aspect of the present invention, there is provided a toggle electric field magnetic random access memory (TEF-RAM) device comprising:

a plurality of memory cells, each memory cell configured to have a resistance state switchable by an applied voltage to the memory cell to create an electric field across a free magnetic layer of the memory cell for switching a magnetization orientation of the free magnetic layer to switch a resistance state of the memory cell;

a read circuit coupled to the plurality of memory cells and configured to perform a read operation on any one of the plurality of memory cells;

a write circuit coupled to the plurality of memory cells and configured to perform a write operation on any one of the plurality of memory cells; and

an error detection module coupled to the read and write circuits and configured to control the read and write circuits to perform the method of error detection in the TEF- RAM device according to the first aspect of the present invention to determine whether an error exists with one or more of the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments of the present invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:

FIG. 1 depicts a schematic cross-sectional view of an example conventional TEF-

RAM cell;

FIG. 2 depicts a schematic drawing of an example conventional single mode memory device;

FIG. 3 depicts a timing diagram of a memory write cycle of the conventional TEF-RAM cell shown in FIG. 1 ;

FIG. 4 depicts a schematic diagram of an example conventional TEF-RAM device;

FIG. 5 depicts a schematic diagram of the example conventional TEF-RAM device shown in FIG. 4 and illustrating the mismatch of the bitline and reference at the two inputs of the sense amplifier;

FIG. 6 depicts a schematic diagram of an example conventional mid-point resistance reference unit;

FIG. 7 depicts a flow diagram of a method of error detection in a TEF-RAM device according to various embodiments of the present invention;

FIG. 8 depicts a flow diagram of a single mode error detection method according to an example embodiment of the present invention;

FIG. 9 depicts a timing diagram of the single mode error detection method in an example implementation according to an example embodiment of the present invention;

FIG. 10 depicts a schematic circuit drawing of a differential mode TEF-RAM device according to various example embodiments of the present invention;

FIG. 11 depicts a schematic circuit drawing of an example write driver (or write circuit) of the differential mode TEF-RAM device of FIG. 10 according to an example embodiment of the present invention;

FIG. 12 depicts a timing diagram of the read and write operations for the differential mode TEF-RAM device of FIG. 10 according to an example embodiment of the present invention; FIG. 13 depicts a schematic circuit drawing of an example sense amplifier (or read circuit) of the different mode TEF-RAM device of FIG. 10 according to an example embodiment of the present invention;

FIG. 14 depicts an example simulation result of the sense amplifier of FIG. 13 in the case of two identical input signals received by the sense amplifier according to an example embodiment of the present invention;

FIGs. 15A and 15B depict flow diagrams of the differential mode error detection method according to two example embodiments of the present invention;

FIG. 16 depicts a timing diagram of the differential mode error detection method according to an example embodiment of the present invention;

FIG. 17 depicts an example architecture of a differential mode TEF-RAM device based on 2T2R bit cell configuration according to an example embodiment of the present invention;

FIG. 18A depicts a schematic drawing of an error detection module for a TEF- RAM device according to various embodiments of the present invention;

FIG. 18B depicts a schematic drawing of a TEF-RAM device according to various embodiments of the present invention;

FIG. 19 depicts a schematic block diagram of an example TEF-RAM device according to an example embodiment of the present invention;

FIG. 20A shows the simulation results of the single mode error detection technique for two example cases of working/functioning cell at high (H) and low (L) resistance states, respectively, according to an example embodiment of the present invention;

FIG. 20B shows the simulation results of the single mode error detection technique for four example cases of hard error cells according to an example embodiment of the present invention;

FIGs. 21 A to 2 ID show various simulation results of the differential error detection technique according the flow diagram of FIG. 15A according to various example embodiments of the present invention; FIG. 22A depicts a flow diagram of an error detection method for a single mode TEF-RAM device using mid-point reference cell based sensing scheme according to various embodiments of the present invention;

FIG. 22B depicts a flow diagram of an error detection process for a single mode TEF-RAM device using mid-point voltage or current based sensing scheme according to various embodiments of the present invention; and

FIG. 22C depicts a flow diagram of an error detection process for the differential mode TEF-RAM according to various embodiments of the present invention. DETAILED DESCRIPTION

[0029] As described in the background, existing toggle electric field magnetic random access memory (TEF-RAM) devices may contain errors (or defects) in one or more memory cells therein, but there does not appear to be existing techniques that are able to detect and/or correct/recover such errors in the memory cells. Therefore, embodiments of the present invention provide method(s) of error detection (or detecting/identifying error(s)) in a TEF-RAM device and TEF-RAM device(s) including an error detection module (or an error detection and recovery module) such that errors in TEF-RAM devices can be detected and appropriate actions may then be taken to address the problem, such as reporting memory cells with hard error (e.g., for subsequent corrections by redundancy replacement and/or error correction coding schemes) and recovering memory cells with soft errors immediately.

[0030] As mentioned in the background, TEF-RAM cell was recently disclosed in Tran et al. (Singapore patent application no. 10201400395Q, which US patent application no. 14/632,442 (US publication no. US 2015/0255135 Al) claims priority to), the contents of both being hereby incorporated by reference in their entirety for all purposes. As an example, FIG. 1 depicts a schematic cross-sectional view of an example TEF- RAM cell 100 disclosed in Tran et al. The TEF-RAM cell 100 comprises a reference magnetic layer structure 102 having a fixed magnetization orientation (as represented by the single-headed arrow 101a or 101b), and a synthetic antiferromagnetic layer structure 103 including a free magnetic layer structure 104 and a coupling magnetic layer structure 106 having a magnetization orientation (as represented by the double-headed arrows 105, 107) that is variable, whereby the reference magnetic layer structure 102 and the synthetic antiferromagnetic layer structure 103 are arranged one over the other. The magnetization orientation 105 of the free magnetic layer structure 104 may be variable from a first direction to a second direction different from the first direction in response to a first voltage (e.g., a short voltage pulse) applied to (or across) the TEF-RAM cell 100 such that a first electric field is provided or generated across the free magnetic layer structure 104, and the switching of the magnetization orientation 105 of the free magnetic layer structure 104 is achieved by means of the electric field effect. Accordingly, the magnetization orientation 105 of the free magnetic layer structure 104 may be variable from the first direction to the second direction in response to the first voltage only or solely. That is, only the first voltage may be required for switching the magnetization orientation 105 of the free magnetic layer structure 104, and other mechanisms or effects such as, for example, spin-transfer torque and/or magnetic field (e.g., an intrinsic or external magnetic bias field, or in-plane magnetic field) may not be required for switching the magnetization orientation 105 of the free magnetic layer structure 104. Furthermore, the magnetization orientation 105 of the free magnetic layer structure 104 may be variable from the second direction to the first direction in response to a second voltage applied to (or across) the TEF-RAM cell 100 (the first voltage and the second voltage having the same polarity) such that a second electric field of the same polarity as the first electric field may be provided or generated across the free magnetic layer structure 104, and the switching of the magnetization orientation 105 of the free magnetic layer structure 104 is again achieved by means of the electric field effect. In this way, bistable magnetization switching may be realized through a unipolar electric field applied to the TEF-RAM cell 100. Therefore, the magnetization orientation 105 of the free magnetic layer structure 104 may be switched from the first direction to the second direction and vice versa using unipolar voltages, meaning, for example, bipolar switching of the magnetization of the free magnetic layer structure 104 may be achieved with respective unipolar voltage pulses. Accordingly, toggle switching of the magnetization orientation 105 of the free magnetic layer structure 104, where the magnetization orientation 105 of the free magnetic layer structure 104 changes to an opposite direction after each voltage pulse, may be achieved. Therefore, the switching of the TEF-RAM cell 100 exhibits toggling characteristic in response to applied short voltage pulses.

[0031] As also mentioned in the background, a single mode memory device/system based on TEF-RAM cells was disclosed in Foong et al. (Singapore patent application no. 10201500289W, which International application no. PCT/SG2015/050520 (International publication no. WO 2016/114718 Al) claims priority to), the contents of both being hereby incorporated by reference in their entirely for all purposes. For example, FIG. 2 depicts a schematic drawing of an example single mode memory device 200 disclosed in Foong et al. The memory device 200 includes a sense amplifier (or read circuit) 202 having a first side and a second side, whereby the second side opposes the first side. The memory device 200 further includes a first array 204A, the first array 204A including a plurality of memory cells (TEF-RAM cells) arranged at the first side of the sense amplifier 202. The memory device 200 may further include a second array 204B, the second array 204B including a plurality of memory cells (TEF-RAM cells) arranged at the second side of the sense amplifier 202. The memory device 200 further includes a first row 206A including a plurality of mid-point reference units arranged at the first side of the sense amplifier 202. The memory device 200 may further include a second row 206B including a plurality of mid-point reference units arranged at the second side of the sense amplifier. Each mid-point reference unit of the first row 206A may be configured to generate a first reference voltage. Each mid-point reference unit of the second row 206B may be configured to generate a second reference voltage. The sense amplifier 202 may be configured to determine a resistance state of a memory cell of the first array 204A based on the second reference voltage. The sense amplifier 202 may also be configured to determine a resistance state of a memory cell of the second array 204B based on the first reference voltage. The memory device 200 may further include further sense amplifiers 202, for example, one sense amplifier for each data channel.

[0032] As shown in FIG. 2, the sense amplifier 202 may be positioned between the first array 204A and the second array 204B. The sense amplifier 202 may be electrically coupled to each of the first array 204A and the second array 204B, for sensing the voltage across a memory cell that is to be read. The plurality of mid-point reference units may be arranged in two rows, namely the first row 206A and the second row 206B. The first row 206 A may be arranged adjacent to the second array 204B while the second row 206B may be arranged adjacent to the first array 204A. Each mid-point reference unit of the first row 206A may be configured to generate a first reference voltage while each midpoint reference unit of the second row 206B may be configured to generate a second reference voltage. Each mid-point reference unit may be configured to provide a midpoint resistance. The mid-point resistance may be at least substantially equal to an average of a high resistance state and a low resistance state. The mid-point reference units may be configured to generate the respective reference voltage based on the respective mid-point resistance. The mid-point reference units of the first row 206A may be at least substantially similar to the mid-point reference units of the second row 206B.

[0033] In operation, the sense amplifier 202 may be configured to determine at least one of a resistance state of a memory cell of the first array 204A based on the second voltage or a resistance state of a memory cell of the second array 204B based on the first voltage. The first voltage used for determining the resistance state of the memory cell of the first array 204A may be generated by a mid-point reference unit in a same column as the memory cell of which its resistance state is to be determined. Similarly, the second voltage used for determining the resistance state of the memory cell of the second array 204B may be generated by a mid-point reference unit in a same column as the memory cell of which its resistance state is to be determined. For example, the sense amplifier 202 may determine the resistance state of a memory cell in the second column of the first array 204A, based on the mid-point reference unit in the second column of the second row 206B. Such an arrangement may facilitate ease of control signal routing. The determination of the resistance state of the memory cell of the first array 204A may be based on a comparison of the voltage of the memory cell with the second reference voltage while the determination of the resistance state of the memory cell of the second array 204B may be based on a comparison of the voltage of the memory cell with the first reference voltage. The sense amplifier 202 may include a first amplifier stage, a second amplifier stage and a plurality of capacitors connected between the first amplifier stage and the second amplifier stage. The plurality of capacitors may be configured, in a first mode of operation, to charge to a voltage corresponding to an offset voltage induced between inputs of the sense amplifier 202. The plurality of capacitors may be further configured, in a second mode of operation, to discharge the plurality of capacitors to counter the offset voltage induced between the inputs of the sense amplifier 202.

[0034] Each memory cell of each of the first array 204A and the second array 204B may be the TEF-RAM cells as disclosed in Tran et al. such as the example TEF-RAM cell as illustrated in FIG. 1. The memory cells in the first array 204A and/or the second array 204B may also be referred to herein as bit cells or main memory cells. Each midpoint reference unit of the first row 206A and the second row 206B may also include a plurality of memory cells, which may also be TEF-RAM cells. The memory cells in the mid-point reference unit may also be referred to herein as mid-point cells or mid-point reference cells. The memory device 200 may further include a write driver (or write circuit) 208 and a controller 210. The write driver 208 may be configured to toggle the resistance state of at least one of a memory cell of the first array 204A or a memory cell of the second array 204B so as to perform a write operation thereto. The write driver 208 may be configured to toggle the resistance state between a high resistance state and a low resistance state. For example, if an existing resistance state of the memory cell is high, the write driver 208 can toggle the resistance state to low, vice-versa. The write driver 208 may be configured to toggle the resistance state of any memory cell only after the resistance state of the memory cell is determined by the sense amplifier. In other words, the sense amplifier 202 may be configured to determine the resistance state of at least one of the memory cell of the first array or the memory cell of the second array before the write driver 208 toggles the resistance state of the memory cell of the first array or the memory cell of the second array (i.e., a read-before-write scheme programming method). The memory device 200 may further include further sense amplifiers 202. The memory device 200 may include further write drivers 208, such as one write driver 208 for each data channel.

[0035] Each of the mid-point reference units may include a plurality of memory cells, such as four memory cells. The write driver 208 may be further configured to toggle the resistance state of the memory cells of each mid-point reference unit. For example, when a mid-point reference unit is in a programming mode, the four memory cells may be connected in parallel. The write driver 208 may be configured to program two memory cells of the four memory cells to a high resistance state and may be further configured to program the other two memory cells to a low resistance state. When the mid-point reference unit is in a read mode, the four memory cells may be arranged in two branches connected in parallel, whereby each branch of the two branches may include a memory cell in the high resistance state connected in series to a memory cell in the low resistance state. With such a circuit arrangement, the mid-point reference unit may provide a midpoint resistance through the four memory cells.

[0036] The controller 210 may be electrically coupled to the sense amplifier 202. The controller 210 may include a plurality of D flip-flops and may be configured to generate internal control signals. The internal control signals may be generated based on the input data and an output signal of the sense amplifier 202. The controller 210 may be further configured to compare an input data to the resistance state of a memory cell, the input data being data that is to be written to the memory cell. The controller 210 may be further configured to generate the internal control signals to toggle the resistance state of the at least one of the memory cell of the first array or the memory cell of the second array if the resistance state of the at least one of the memory cell of the first array or the memory cell of the second array is not at least substantially matched to the input data. For example, if the input data is binary logic "1" and the resistance state of the memory cell to be written to is low, the controller 210 may generate an internal control signal for controlling the write driver 108 to toggle the resistance state of the memory cell to high resistance state. On the other hand, if the resistance state of the memory cell to be written to is already high, the controller 210 may generate an internal control signal to control the write driver 208 not to toggle the resistance state of the memory cell or alternatively the controller 210 may not generate any internal control signal for operating the write driver 108.

[0037] The internal control signals may be used to address the selected memory cell, control the write driver and/or control the sense amplifier 202. The controller 210 may be further configured to sample rising edges of a clock signal and falling edges of the clock signal, and may be further configured to align the internal control signals to the rising edges of the clock signal and the falling edges of the clock signal. The controller 210 may include a plurality of digital delay elements configured to align edges of the internal control signals to the rising edges of the clock signal and the falling edges of the clock signal.

[0038] FIG. 3 shows a timing diagram 300 of a memory write cycle of a TEF-RAM cell and also depicts various internal control signals for a TEF-RAM cell. The internal control signals may include a clock signal (CLK) 301, a precharge signal (precharge) 302, a sense amplifier 202 enable signal (saen) 304, a write enable signal (wen) 306 and a discharge signal (discharge) 308. Due to the toggling behavior of TEF-RAM cell, a write pulse may be able to switch the memory cell to either high resistance or low resistance based on the previous state of the memory cell. Therefore, a read-before-write method/scheme may be required for the write operation of TEF-RAM cell to avoid write error. In other words, the memory cell may be read before the memory cell is written to. The sense amplifiers employed in the write scheme/method may be common for both write and read operations and therefore, additional sensing circuits may not be required. The timing diagram 300 shows the internal control signals CLK 301, precharge 302, saen 304, wen 306 and discharge 308 for a single write cycle. The write cycle may have a duration of two clock cycles or in other words a duration of two periods. The write cycle may be divided into three phases, namely a precharge phase 310, a read phase 312 and a write phase 314. The first half of the first clock period may be the precharge phase 310. During the precharge phase 310, a precharge pulse may be generated as part of the precharge signal 302 and the selected bitline may be pulled to a precharge voltage. The precharge voltage may be about 0.5V. The next one clock period may be the read phase 312. During the read phase 312, the sense amplifier 202 enable signal 304 may be high so as to activate the sense amplifier 202. A read current may be steered towards the selected memory cell, and a mirrored read current of the same value may be steered towards the mid-point reference unit. The direction of the read current may be of the same polarity or reversed polarity as compared to the write current. The read current may be driven to the memory cell from the reversed direction as compared to the write current to prevent read disturbance. The sense amplifier 202 may then compare the voltage at the inputs to the voltage generated by the midpoint reference unit across the mid-point resistance generated by the mid-point reference unit, to determine the resistance state of the selected memory cell. During the write phase 314, the controller 210 may decide whether a write enable pulse of half-clock period should be switched high based on read output to toggle the resistance state to match with the input data.

[0039] FIG. 4 shows a schematic diagram of a TEF-RAM device 400 including various circuit blocks which may be provided for operating the memory (TEF-RAM) cell 420. The circuit blocks may perform functions/operations including read and write, as well as provide the corresponding control signals. In other words, the circuit blocks may control the write and read of a memory cell 420 and condition the bitlines, such as bitline precharge and discharge blocks, and the corresponding control signals. The circuit blocks may include a read/write controller 210, a bitline precharge circuit 422, a bitline discharge circuit 424, a write driver 426, a sense amplifier 428 and a mid-point reference unit 418. The read/write (R/W) controller 210 may be configured to generate the internal control signals, e.g. precharge (prech) 302, discharge (disch) 308, sense amplifier enable (saen) 304 and write enable (wen) signals 306, which may be aligned to the clock edges. The R/W controller 210 may also decide on the need to generate the internal write enable (wen) 316 pulse based on the input data (din) 430 and the sensed data (dsa) 432 from the memory cell 420. A clamping transistor 434 may be connected between the bitline and the sense amplifier 428 or write driver 426 to prevent read disturbance to the memory cells 420 by connecting its gate to a clamp voltage (Vclamp) 436 during read and to prevent overdriving the memory cell to avoid breakdown of the memory during write. During write, the gate of the clamping transistor is connected to another voltage, e.g. a boosted voltage 438, to provide the voltage required to toggle the memory state. The boosted voltage 438 may compensate the gate-to-source voltage or Vgs drop of the clamping transistor 434 during write operation.

[0040] FIG. 5 depicts a schematic diagram of the TEF-RAM device 400 shown in FIG. 4 to illustrate the mismatch of the bitline and reference at the two inputs of the sense amplifier 428. The schematic diagram 400 depicts the difference in parasitic capacitance and coupling between the bitline and the mid-point reference unit 418. One input of the sense amplifier 428 may be connected to the selected memory cell 420 and the other input may be connected to the selected mid-point reference unit 418. The mismatch may result due to the difference in parasitic capacitance of the bitline and the reference line and the signal coupling effect of the memory cell 420 and that of the mid-point reference unit 418. The mismatch may generate an offset voltage for the sense amplifier 428, which may result in a read error.

[0041] FIG. 6 depicts a schematic diagram of an example mid-point resistance reference unit 600. The midpoint resistance reference unit 400 may be the midpoint reference unit 418 shown in FIGs. 4 and 5. The midpoint resistance reference unit 400 may include four TEF-RAM cells 420 and a number of pass transistors or control switches. During the read phase, the midpoint resistance may be formed by two parallel branches of a TEF-RAM cell 420 in a high-resistance state and a TEF-RAM cell 420 in a low-resistance state in series based on the following equation:

[0042] The pass transistors may be sized large enough such that their respective on- resistances are negligible compared to the resistance of the memory cells 420. The midpoint resistance reference circuit 600 may be capable of tracking temperature changes by employing memory cells 420. During read, read ref is logic ' , and read refb is logic Ό'. The mid-point reference unit may be configured to generate the mid-point resistance. When read ref is logic '0' and read_refb is logic ' 1 ', the mid-point reference unit may be in the mid-point programming mode. During the mid-point programming mode, the midpoint resistance reference unit 600 may be configured such that it is broken down to four 1 transistor/selector + 1 memory cell (1T1R) units connected in parallel. Therefore, the four 1T1R units maybe be programmed separately with the control of the wordlines of the four selectors (wl refl, wl_ref2, wl_ref3 and wl_ref4).

[0043] However, as mentioned in the background, adopting a mid-point reference sensing scheme/method for reading the memory cells may lead to high capacitive mismatch at the two input terminals of the sense amplifier 428 of the TEF-RAM device as illustrated in FIG. 5 (single mode TEF-RAM device), thereby compromising the limited sensing margin. In addition, the mid-point reference unit 418 for providing a reference voltage to the sense amplifier for reading the memory cells may include four TEF-RAM cells and a number of pass transistors or control switches as illustrated in FIG. 6, and such components may have reliability and accuracy issues. For example, when one or more of the TEF-RAM cells in the mid-point reference unit has an error (e.g., hard or soft error), the resulting reference voltage generated by the mid-point reference unit for use by the sense amplifier as a comparison to read the memory cells may become inaccurate (e.g., generate offset reference voltage) and the reading output data may thus be incorrect. For example, a hard error exists when a resistance state of the memory cell is unswitchable by a write operation configured for switching the resistance state of the memory cell, and a soft error exists when a first memory element and a second memory element of a differential memory cell are at the same resistance state (since for differential memory cells, the first and second memory elements should be at opposite states. Differential mode TEF-RAM may also suffer from hard or soft error. However, there does not appear to be existing techniques that are able to detect and/or correct/recover such errors (or defects) in TEF-RAM cells. Therefore, embodiments of the present invention provide method(s) of error detection in a TEF-RAM device, including a single mode TEF-RAM device (single mode error detection technique/method) such as described hereinbefore with reference to FIGs. 1 to 6, and a differential mode TEF-RAM device (differential mode error detection technique/method). Further embodiments of the present invention are also able to correct/recover certain types of errors in the TEF-RAM cells, such as soft errors.

[0044] According to various embodiments of the present invention, a single mode error detection method is provided for identifying/detecting error(s) in a TEF-RAM device, and in particular, identifying/detecting hard error cells involving, e.g., open, short and unswitchable memory (TEF-RAM) cells in the single-mode TEF-RAM device. Memory cells which are working/functioning properly (i.e., non-defective) in the TEF- RAM device remain unchanged (i.e., no actions required to be taken thereon). In various embodiments, the method may involve two normal write operations and two normal read operations. The read operation adopts a mid-point reference scheme/method with midpoint cells or mid-point voltage/signal (e.g., as described with reference to FIGs. 2 to 6). As will be described in further details later, the read-write-read sequence in the single mode error detection method developed according to various embodiments of the present invention is able to differentiate hard error memory cells from working/functioning memory cells based on the status/state of the memory cells after a first write operation. A second write operation may then be performed on the memory cells determined to be working/functioning to flip/switch the status/state of such memory cells to their original state. It will be appreciated that working/functioning memory cells refer to memory cells that are working/functioning properly (i.e., as intended or as configured to), that is, non- defective. For example, defective memory cells may include open, short and/or unswitchable memory cells. For example, the single mode error detection method may be applied for error detection on memory cells in the main memory unit/array (e.g., first and/or second arrays 204A, 204B in FIG. 2) (which may be referred to herein as bit cells or main memory cells) and memory cells in the mid-point reference unit/section (which may be referred to herein as mid-point cells or mid-point reference cells).

[0045] According to various embodiments of the present invention, a differential mode error detection technique/method is provided for identifying error(s) in a TEF- RAM device, such as identifying/detecting error(s) in mid-point reference cells of a single mode TEF-RAM device (since the mid-point reference cells may be configured in differential mode architecture) and/or main memory cells of a differential mode TEF- RAM device. For example, if the sensing method/scheme in a single mode TEF-RAM device is based on mid-point reference cells, the differential mode error detection technique may be applied on the mid-point reference cells first and then followed by applying the single mode error detection technique on main memory cells. On the other hand, if the sensing method scheme in the single mode TEF-RAM device is based on mid-point voltage or current (i.e., without mid-point reference cells), the single mode error detection technique is applied on the main memory cells. In various embodiments, the differential mode error detection technique/method seeks to identify/detect hard error bit cells in differential TER-RAM devices, such as open, short, and/or unswitchable bit cells and to report on such errors. The method also seeks to identify/detect soft error bit cells in differential TEF-RAM devices in which, for example, the two memory elements in the bit cell are in the same resistance states, and for example, to recover/rectify them to the default or working/functioning state (e.g., a Low-High (LH) state or a High-Low (HL) state) such that they become usable or reusable. Working/functioning memory or bit cells in which the two memory elements are already in differential states remain unchanged (i.e., no actions required to be taken thereon). In various embodiments, the differential mode error detection method may include five controlled read and three controlled write operations. A write circuit (or write driver) may be provided to perform a write operation (or program) on either one or both of the memory elements in the target memory (or bit) cells for states checking, and a read circuit (or sense amplifier) with controllable bias towards either input signal may be provided to perform a read operation on the target memory (or bit) cell to ensure that a deterministic output can be generated based on which a correct classification of the memory cell can be performed.

[0046] In various embodiments, operations for differential TEF-RAM devices associated with the differential mode error detection technique are also provided. In an example embodiment, differential read and write operations are performed on a pair of memory (TEF-RAM) elements in each memory (or bit) cell. During initialization, the two memory elements may be set to differential states using the differential mode error detection technique according to various embodiments before product testing and shipping. During a normal write operation, the write driver may deliver two independent voltage pulses to each of the two memory elements and programs them at the same time to maintain their differential states. During a normal read operation, two bit lines of the TEF-RAM device accessing the two memory elements may be pre-charged by the read driver (sense amplifier) and dis-charged through the two memory elements. The sense amplifier may be configured to capture the voltage difference between the two memory cells and to read out the stored differential information.

[0047] FIG. 7 depicts a flow diagram of a method 700 of error detection (or detecting/identifying error(s)) in a TEF-RAM device according to various embodiments of the present invention. For example and without limitation, the TEF-RAM device may be a single mode or differential mode TEF-RAM device as described herein. The method 700 comprises a step 702 of performing a first read operation on a memory cell of the TEF-RAM device to obtain a first read output of the memory cell (TEF-RAM cell), a step 704 of performing a first write operation on the memory cell after the first read operation, a step 706 of performing a second read operation on the memory cell after the first write operation to obtain a second read output of the memory cell, and a step 708 of determining whether an error exists with the memory cell based on the first read output and the second read output. [0048] In various embodiments, the first read operation may be performed by a read circuit (e.g., sense amplifier) of the TEF-RAM device as described hereinbefore, and the first read output of the memory cell may be a resistance state of the memory cell (e.g., High or Low state corresponding to binary logic 1 or 0). For example, the resistance state of the memory cell may be determined by the sense amplifier based on a comparison of the voltage of the memory cell with a reference voltage. The second read operation may also be performed by the read circuit in the same manner as the first read operation.

[0049] In various embodiments, the first write operation may comprise applying a voltage to the memory cell to create an electric field across a free magnetic layer of the memory cell for switching a magnetization orientation of the free magnetic layer to switch a resistance state of the memory cell. As described hereinbefore, the switching of the TEF-RAM cell exhibits toggling characteristic in response to applied short voltage pulses, and in particular, the magnetization orientation of the free magnetic layer structure of the TEF-RAM cell may be switched or toggled by an electric field created via a voltage applied to the memory cell. Therefore, for a working/functioning memory cell, performing the first write operation on the memory cell would switch or toggle the magnetization orientation of the free magnetic layer of the TEF-RAM cell and thus its resistance state.

[0050] In various embodiments, the error comprises a first type of error (e.g., a hard error), and determining whether an error exists with the memory cell comprises determining whether the first type of error exists with the memory cell based on whether the first read output and the second read output are the same or different. In various embodiments, determining whether the first type of error exists with the memory cell comprises determining that the first type of error exists with the memory cell when/if the first read output and the second read output obtained are the same, and determining that the first type of error does not exist with the memory cell when/if the first read output and the second read output obtained are different. For example, the first read output and the second read output may be the same when/if both are at a first state, or both are at a second state, and the first read output and the second read output are different when/if the first read output is at the first state and the second read output is at the second state, or vice versa. In various embodiments, the first state may be a high state or a binary logic 1 state, and the second state may be a low state or a binary logic 0 state. In various other embodiments, the first state may be a low state or a binary logic 0 state, and the second state may be a high state or a binary logic 1 state.

[0051] In various embodiments, the method 700 may be a single mode error detection method/technique for detecting whether there exists an error with one or more memory cells in a single mode TEF-RAM device. For better understanding and as an example illustration only, a single mode error detection method/technique according to an example embodiment of the present invention will now be described. However, it will be appreciated to a person skilled in the art that the present invention is not limited to the single mode error detection method described in the example embodiment.

[0052] In the example embodiment, the single mode error detection method seeks to detect hard error cells in the single mode architecture that mainly includes the memory (or bit) cells in the main memory array (e.g., first array and/or second array 204A/204B shown in FIG. 2) of the TEF-RAM technology. For example, the bit cells may be classified into two categories according to their resistance states as shown in Table 1 below. In this regard, working/functioning cells include or consists of working/functioning cells having a high (H) or low (L) resistance. On the other hand, hard error cells include cells having an open (O) state, a short (S) state, a high resistance but unswitchable/faulty (H _F ), and low resistance but unswitchable/faulty (L _F ). For example, an open state may correspond to an open circuit state (e.g., a very high resistance state (e.g., resistance at open state (RQ) » resistance at high state (RH)) of the memory cell that could have resulted from fabrication errors, cell breakdown, and so on) and a short state may correspond to a short circuit state (e.g., a very low resistance (e.g., resistance at short state (Rs) « resistance at low state (R _L )) of the memory cell that could also have resulted from fabrication errors, cell breakdown, and so on).

Table 1 - Possible bit cell classification in the single mode error detection technique [0053] FIG. 8 depicts a flow diagram 800 of the single mode error detection method by way of an example illustration only for better understanding and without limitation. In the following description of the single mode error detection method, the possible bit cell states are provided in parenthesis after each step to facilitate a better understanding of the method and flow diagram. As shown in FIG. 8, a first read operation 802 on a memory cell of the TEF-RAM device may be performed by a read circuit (e.g., sense amplifer) of the TEF-RAM device (e.g., based on mid-point reference sensing as described hereinbefore) to obtain a first read output (SA1) of the memory cell. Subsequently, at step 804, it is determined/judged whether SA1 is logic 1 or 0. If SA1 equals l 'bl (i.e., 1 bit binary 1) (thus possible bit cell states: H, H _F , O), a write operation 806 is performed (thus possible bit cell states: L, Hp, O). A second read operation 808 is then performed to obtain a second read output (SA2). Subsequently, at step 810, it is determined/judged whether SA2 is logic 1 or 0. If SA2 equals l 'bl, then a hard error (O and/or Hp) associated with the memory cell being tested is detected/determined. On the other hand, if SA2 equals I 'bO (i.e., 1 bit binary 0), the memory cell is determined to be working/functioning properly and a second write operation 812 may then be performed to toggle the working cell back to its original high (H) resistance state. At step 804, if SA1 equals I'bO (thus possible bit cell states: L, L _F , S), a write operation 814 is performed (thus possible bit cell states: H, Lp, S). A second read operation 816 is then performed to obtain a second read output (SA2). Subsequently, at step 818, it is determined/judged whether SA2 is logic 1 or 0. If SA2 at step 818 equals I 'bO, then a hard error (S and/or Lp) associated with the memory cell being tested is detected. On the other hand, if SA2 at step 818 equals l 'bl, the memory cell is determined to be working/functionly properly and a second write operation 812 may then be performed to toggle the working memory cell back to its original low (L) resistance state.

[0054] Accordingly, the single mode error detection method advantageously enables the detection of hard error cells in the single mode TEF-RAM device. Furthermore, from the example illustration shown in FIG. 8, it can be observed that whether a hard error exists with the memory cell can be determined based on whether the first read output and the second read output are the same or different. [0055] FIG. 9 depicts a timing diagram of the single mode error detection technique in an example implementation according to an example embodiment of the present invention. In the example embodiment, the method/process may be activated/initiated by an error check enable (ecen) signal that generates an internal reset signal (rn) which in turn starts a 3 -bit clock counter. There is one clock latency between the assertion of the ecen signal and the first valid output of the counter 3'b001 (i.e., 3 bit binary 001). In various embodiments, in order to minimize/remove glitches, all output signals are sampled by registers that lead to an extra synchronization clock before the first read signal/pulse (read) is output. All subsequent output signals are synchronized to but one- clock shifted from the counter output. As can be seen from FIG. 9, the counter is reset after the output of 3'bl l0 and re-count from 3'b000. Therefore, seven valid counter outputs may be produced within one detection cycle, in which two read, two write and one error report operations may be performed for example. The next cycle starts when counter output becomes 3'b001 again. When the ecen signal is deactivated, all control signals go to low.

[0056] In various embodiments, the TEF-RAM device may be a differential mode TEF-RAM device, and the method 700 as shown in FIG. 7 may be a differential mode error detection method/technique for detecting whether there exists an error with one or more memory cells in the differential mode TEF-RAM device. The memory cell in the differential mode TEF-RAM device may comprise a first memory element and a second memory element differentially coupled together for storing differential data (e.g., see FIG. 10 to be described later below). In various embodiments, the differential mode error detection technique seeks to detect hard errors and/or soft errors (as well as recovering soft errors) in the differential mode architecture which, for example, includes the mid- point reference cells in the single mode TEF-RAM device and the main memory cells in the differential mode TEF-RAM device.

[0057] In various embodiments, in the differential mode error detection method, performing the first read operation in the method 700 as shown in FIG. 7 may comprise performing at least two read operations on the memory cell to obtain at least two read outputs of the memory cell. In this regard, a first of the at least two read operations is performed to obtain a first of the at least two read outputs of the memory cell, and a second of the at least two read operations is performed based on the first of the at least two read outputs to obtain a second of the at least two read outputs of the memory cell. Therefore, the second of the at least two read outputs may correspond to the first read output of the memory cell described hereinbefore with respect to FIG. 7.

[0058] In various embodiments, the second of the at least two read operations is selected from one of a read operation with a negative bias and a read operation with a positive bias based on the first of the at least two read outputs of the memory cell. Performing read operations with negative and positive bias, and the associated exemplary circuit configuration, will be described later below.

[0059] In various embodiments, the second of the at least two read operations is selected to be the read operation with a negative bias when the first of the at least two read outputs of the memory cell obtained is at a first state. On the other hand, the second of the at least two read operations is selected to be the read operation with a positive bias when the first of the at least two read outputs of the memory cell obtained is at a second state. As mentioned hereinbefore, in various embodiments, the first state may be a high state or a binary logic 1 state, and the second state may be a low state or a binary logic 0 state. In various other embodiments, the first state may be a low state or a binary logic 0 state, and the second state may be a high state or a binary logic 1 state.

[0060] In various embodiments, the second read operation is also selected from one of the read operation with a negative bias and the read operation with a positive bias.

[0061] In various embodiments, the error comprises at least one of a first type of error (e.g., a hard error) and a second type of error (e.g., a soft error). In various embodiments, determining whether an error exists with the memory cell may comprise determining whether the first type of error or the second type of error exists with the memory cell based on whether the at least two read outputs of the memory cell and the second read output are the same or different.

[0062] In various embodiments, determining whether the first type of error or the second type of error exists with the memory cell comprises determining that the first type of error exists with the memory cell when the at least two read outputs and the second read outputs of the memory cell obtained are the same. In addition, determining whether the first type of error or the second type of error exists with the memory cell may comprise determining that neither the first type of error nor the second type of error exist with the memory cell when the at least two read outputs of the memory cell obtained are the same and the second read output of the memory cell is different to the at least two read outputs.

[0063] In various embodiments, when the at least two read outputs are different, the first write operation may be performed only on one of the first and second memory elements, and a third read operation may be performed on the memory cell after the second read operation to obtain a third read output of the memory cell. In various embodiments, a fourth read operation may be performed on the memory cell after the third read operation to obtain a fourth read output of the memory cell, and determining whether the first type of error or the second type of error exists with the memory cell is further based on at least one of the third and fourth read outputs.

[0064] In various embodiments, when the at least two read outputs obtained are different, the first write operation is performed only on the first memory element, the second read operation is performed with a positive bias, and a second write operation is performed on both the first and the second memory elements before the third read operation is performed when/if the second read output obtained is at the second state (e.g., a low state or a binary logic 0 state), and a third write operation on both the first and the second memory elements before the fourth read operation is performed when/if the third read output obtained is at the first state (e.g., a high state or a binary logic 1 state). Based on the above, the first type of error can be determined to exist with the memory cell when the third read output obtained is at the second state or when the fourth read output obtained is at the first state, and the second type of error can be determined to exist with the memory cell when the fourth read output obtained is at the second state. For better understanding, the above will be described in further details and with reference to a flow diagram in FIG. 15A later below.

[0065] In various other embodiments, when the at least two read outputs obtained are different, the first write operation is performed only on the second memory element, the second read operation is performed with a negative bias, and a second write operation is performed on both the first and the second memory elements before the third read operation when/if the second read output obtained is at the first state, and a third write operation is performed on both the first and the second memory elements before the fourth read operation when/if the third read output obtained is at the second state. Based on the above, the first type of error can be determined to exist with the memory cell being tested when the third read output obtained is at the first state or when the fourth read output obtained is at the second state, and the second type of error can be determined to exist with the memory cell when the fourth read output obtained is at the first state. For better understanding, the above will be described in further details and with reference to a flow diagram in FIG. 15B.

[0066] For better understanding, a differential mode TER-RAM device (and various components thereof) and a method of detecting an error in the different mode TER-RAM will now be described according to various example embodiments of the present invention. However, it will be appreciated to a person skilled in the art that the present invention is not limited to the specific forms/layouts/configurations shown, which can be modified as appropriate/desired for various purposes without departing from the scope of the present invention.

[0067] FIG. 10 depicts a schematic circuit drawing of a differential mode TEF-RAM device 1000 according to various example embodiments of the present invention. As shown, the differential mode TEF-RAM device 1000 comprises a write driver (or write circuit) 1002, a sense amplifier (or read circuit) 1004, and a memory cell (or bit cell) 1006 coupled to the write driver 1002 and sense amplifier 1004. As shown, the memory cell 1006 comprises or consists of two TEF-RAM elements 1007, 1008 and two transistors connected in a 2T2R (i.e., dual mode) configuration. In the example embodiment of FIG. 10, the memory cell 1006 is arranged to be accessed by two bit lines (bll, blr) 1010, 1012, two source lines (sll, sir) 1014, 1016 and one word line (wl) 1018. Each bit line is connected to the write driver 1002 and the sense amplifier 1004 through a NMOS column switch 1020 controlled by column selection signal (col). Each bit line is also discharged when unselected through another NMOS transistor 1024 controlled by the differential signal (colb). The differential mode TEF-RAM device 100 features unidirectional writing, therefore both source lines 1014, 1016 are connected to ground. The two TEF-RAM elements 1007, 1008 are initialized to be in differential states. For example, during a write operation, both of the TEF-RAM elements 1007, 1008 are toggled to maintain the differential states, and during a read operation, the difference in resistance between the two TEF-RAM elements 1007, 1008 is sensed. Therefore, a faster and more reliable sensing can be achieved than, for example, a mid-point reference based sensing technique as used in a single mode TER-RAM device due to the doubled sense margin.

[0068] FIG. 11 depicts a schematic circuit drawing of an example write driver (or write circuit) 1002 of the differential mode TEF-RAM device 1000 according to an example embodiment of the present invention. As shown, the write driver 1002 is configured to receive two independent write pulses (wtl and wtr) to program the two TEF-RAM elements 1007, 1008 in the memory cell (bit cell) 1006. The write driver 1002 comprises a pair of tri-state buffers 1 1 10 controlled by two independent write signals (wtl and wtr) for driving the two master bit lines (mbll and mblr) 1030, 1032, which are further connected to the selected bit cell 1016 through column switches 1020, 1024. The write driver 1002 further comprises another pair of tri-state buffers 1120 connected to the master bit lines (mbll and mblr) 1030, 1032 and are configured to pull down the master bit lines (mbll and mblr) 1030, 1032 when pull-down signals (pdl and pdr) are asserted.

[0069] FIG. 12 depicts a timing diagram of the read and write operations for the differential mode TEF-RAM device according to an example embodiment for illustration purpose only. As shown in the timing diagram, the write operation may last two clock cycles consisting of a 1.5 clock cycle read operation and a half clock cycle write pulse generation. The write pulses (wtl and wtr) that program the first and second (e.g., left and right) memory elements respectively are generated at the last half clock cycle of the two- clock write. In a normal write operation, if the stored data (dsa) differs from the data to be written (din), the write pulses (wtl and wtr) are asserted at the same time to toggle both memory elements so as to maintain their differential states (while pull-down signals (pdl and pdr) remain low). If din equals dsa, the write pulses (wtl and wtr) are not generated and pull-down pulses/signals pull down the master bit line to prevent an accidental write. In the error detection and recovery mode, when writing of only one memory element (either one of the two memory elements of the bit cell but writing to the left element is illustrated in FIG. 12 as an example) in the selected bit cell is required, only write signal (wtl) is generated and pull-down signal ipdr) pulls down right master bit line (mblr) 1032.

[0070] The sense margin of a sense amplifier must be large enough (e.g. >20 mV) to achieve a correct and stable read operation. In the event of a soft error when the sense margin is nearly zero, a normal sense amplifier will produce an indeterministic output, thereby impeding consistent decision making. FIG. 13 depicts a schematic circuit drawing of an example sense amplifier (or read circuit) 1004 of the different mode TEF- RAM device 1000 according to an example embodiment of the present invention. In particular, a cross-coupled voltage sense amplifier 1004 is provided with controllable bias towards either the positive input (inp) or the negative input (inn). The controllable bias may be realised using six transistors, that is, three transistors on each input branch. As shown, the sense amplifier 1004 is configured such that transistors MN5, MP4 and MP6 are controlled by a pair of differential signals (nben and nbenb), providing bias towards negative input (inn). With such a configuration, when nben is low, transistor MN5 is turned off, transistor MP6 is turned on and transistor MP4 is turned off, thereby disabling the bias feature. On the other hand, when nben is high, transistor MN5 is turned on, transistor MP6 is turned off, and positive input (inp) is applied on the gate of transistor MP4. As a result, extra current will be injected into the drain of transistor MN2 in addition to the current pumped by transistor MP2. The extra current has the same effect of a smaller inp, therefore provides bias towards the negative input (inn). The same or similar analogy applies to transistors MN6, MP5 and MP7 that controls the bias towards the positive input (inp). In various embodiments, the bias strength may be controlled by configuring/selecting the size of transistors MP4 and MP5 that determine the amplitude of the additionally steered currents. In various embodiments, the two transistors are carefully sized such that the bias strength is equivalent to half of the designed sense margin under normal condition. Furthermore, to ensure symmetrical bias, the size of the two transistors are made the same. As will be appreciated, biased sensing is only performed in some read operations of the error detection mode and/or the error recovery mode according to various embodiments of the present invention. The normal read operation (i.e., without bias) and the sub-read operation(s) which may be included in all write operations are carried out without bias. [0071J FIG. 14 depicts an example simulation result of the sense amplifier 1004 in the case of two identical input signals received by the sense amplifier 1004. In the example simulation, a number of read operations were carried out as indicated by the signal sen within three phases, namely, no bias, positive bias and negative bias as indicated by the pair of differential signals (pben and nberi). It can be observed that the output signal (dout) shows indeterministic characteristic when bias was not activated. However, when pben is enabled, dout is biased towards the positive input, and when nben is enabled, dout is biased towards the negative input, thereby demonstrating the capability of the sense amplifier 1004 to perform a normal read operation (i.e., without bias), a read operation with a positive bias, and a read operation with a negative bias.

[0072] As described hereinbefore, in various embodiments, the differential mode error detection technique/method is able to detect hard errors and/or soft errors (as well as recovering soft errors) in the differential mode architecture which, for example, includes the mid-point reference cells in single mode TEF-RAM device and main memory cells in the differential mode TEF-RAM device. For example, the bit cells may be classified into various categories according to their resistance states as shown in Table 2 below.

Table 2 - Bit cell classification in the differential mode error detection technique

[0073] In Table 2, H and L represent for high and low resistance states respectively, O and S represent open and short devices/elements respectively, and Hp and Lp stand for non-switchable (faulty) cells at H and L states respectively. In this regard, the normal read outputs of the working cells, and the first and second cases of hard error cells (HE- C 1 and HE-C2) are deterministic, where they do not change with the polarities of the biased read operation. On the other hand, the normal read outputs of soft error cells and the third case of hard error cells (HE-C3) are indeterministic, where the read outputs are directly determined by the polarities of the biased read operation.

[0074] FIG. 15A depicts a flow diagram 1500 of the differential mode error detection method by way of an example illustration only for better understanding and without limitation. Similar to when describing the single mode error detection method with reference to FIG. 8, the possible bit cell states are provided in parenthesis after certain steps to facilitate a better understanding of the method and flow diagram. As a first step 1502, a normal read operation (e.g., corresponding to a first of the at least two read operations as described hereinbefore) is performed on the memory cell being tested to obtain a read output SA1 (e.g., corresponding to a first of the at least two read outputs as described hereinbefore). Subsequently, at step 1504, it is determined/judged whether the read output SA1 is at logic 1 or 0. If the read output SA1 is l'bl (thus possible bit cell states: HL, HH, LL, HE-C1, and HE-C3), a read operation 1506 (e.g., corresponding to a second of the at least two read operations as described hereinbefore) with a negative bias is performed to obtain a read output SA2 (e.g., corresponding to a second of the at least two read outputs or a first read output as described hereinbefore). Subsequently, at step 1508, it is determined whether the read output SA2 is at logic 1 or 0. If the read output SA2 is l 'bl (thus possible bit cell states: HL, HE-C1), a write operation 1510 (e.g., corresponding to a first write operation as described hereinbefore) on both memory elements in the bit cell is performed (possible bit cell states: LH, OH, OL, OS, OH _F , OL _F , LS, HS, H _F S, L _F S, LL _F , H _F L _F , H _F H). A read operation (e.g., corresponding to a second read operation as described hereinbefore) with a positive bias 1512 is subsequently performed to obtain a read output SA3 (e.g., corresponding to a second read output as described hereinbefore) of the bit cell. Then, at step 1514, it is determined/judged whether the read output is at logic 1 or 0. If read output SA3 is still 1 'bl (thus possible bit cell states: OH, OL, OS, OH _F , OLp, LS, HS, H _F S, L _F S, LL _F , H _F L _F , H _F L), the bit cell is determined to have a hard error. On the other hand, if read output SA3 is 1 'b0 (thus possible bit cell states: LH), the bit cell is determined to be a working cell and a write operation 1515 is performed on both memory elements of the bit cell to return the memory elements to their original states. For example and without limitation, the above steps may seek to differentiate the working cell HL from the hard error HE-C1 cells. In this regard, the types of cells that could cause misclassification in HE-C1 category are HLF, HFLF, and HpL cells, and the remaining types of cells' read outputs (i.e., types of cells in HE-C1 category other than HLp, HpLp, and HpL cells, e.g., OH, OL, OS, OH _F , OLp, HS, LS, HpS, L _F S cells) would not change regardless of what types of write operations are performed (i.e., fixed at I 'M). Therefore, the above steps seek to differentiate HL cell from the HLp, HpLp, and HpL cells by writing both elements and performing a positive bias read. For example, if the write operation is only performed on the left memory element, HL cell would not be differentiated from HLp cell and if the write operation is only performed on the right memory element, HL cell would not be differentiated from HpL. Accordingly, different categories/types of cells are able to be differentiated/classified, and thus errors in memory cells are able to be detected.

[0075] If read output SA1 equals 1 'b0 (thus possible bit cell states: LH, HH, LL, HE- C2, and HE-C3), a read operation 1516 (e.g., corresponding to a second of the at least two read operations as described hereinbefore) with positive bias is performed to obtain a read output SA2. Subsequently, at step 1518, it is determined/judged whether the read output S A2 is at logic 1 or 0. If the read output SA2 is 1 'b0 (thus bit cell states: LH, HE- C2), a write operation 1520 (e.g., corresponding to a first write operation as described hereinbefore) is performed on both memory elements (thus possible bit cell states: HL, LO, HO, SO, HpO, LpO, SH, SL, SH _F , SL _F , LpH, L _F H _F , HH _F ). A read operation 1522 (e.g., corresponding to a second read operation as described hereinbefore) with a negative bias is then performed. At step 1524, it is determined/judged whether the read output SA3 is at logic 1 or 0. If read output SA3 is l 'bO (thus bit cell states: LO, HO, SO, H _F 0, L _F 0, SH, SL, SH _F , SL _F , L _F H, L _F H _F , HH _F ), the bit cell is determined to have a hard error. On the other hand, if read output SA3 is l 'bl (thus possible bit cell states: HL), it is a working cell and a write operation 1525 is performed to both memory elements of the bit cell to return the memory elements to their original states. For example and without limitation, the above steps may seek to differentiate the working cell LH from the HE-C2 cells. In this regard, the types of cells that could cause misclassification in HE-C2 category are L _F H, L _F H _F , and LH _F , and the remaining types of cells' read outputs (i.e., types of cells belonging to HE-C2 category other than L _F H, L _F H _F , and LH _F cells, e.g., HO, LO, SO, H _F 0, LpO, SH, SL, SHp, SLp cells) would not change regardless of what types of write operations are performed (i.e., fixed at 1 'b0). Therefore, the above steps seek to differentiate LH cell from the LFH, LFHF, and LHF cells by writing both elements and performing a negative bias read. For example, if a write operation is only performed on the left device, LH cell would not be differentiated from LHp cell and if the write operation is only performed on the right device, LH cell would not be differentiated from LpH cell. Accordingly, different categories/types of cells are able to be differentiated/classified, and thus errors in memory cells are able to be detected.

[0076] If read outputs SA1 and SA2 at steps 1504 and 1508/1518 are different, this indicates that a soft bias towards the opposite input changes the sense amplifier output, indicating that the sense margin is close to zero (thus possible bit cell states: SE and HE- C3). Subsequently, a write operation 1530 (e.g., corresponding to a first write operation as described hereinbefore) on the first or left memory element is performed (thus possible bit cell states: LH, HL, OO, SS, LHp, HLp, H _F H _F , L _F L _F , H _F H, L _F L), followed by a read operation 1532 (e.g., corresponding to a second read operation as described hereinbefore) with a positive bias. For example and without limitation, this group of cells has indeterministic read output, therefore the first write operation is only performed on one of the memory elements to recover the soft error cells to working states. Then, at step 1534, it is determined/judged whether the read output SA3 is at logic 1 or 0. If the read output SA3 is 1 'bO (thus possible bit cell states: LH, LH _F ) (for example, the positive bias read can quickly single out the two types of cells LH, LH _F from the remaining types of cells in this category (e.g. SE and HE-C3 cells)), a write operation 1536 (e.g., corresponding to a second write operation as described hereinbefore) on both elements is performed (bit cell states: HL, HH _F ) (for example, to differentiate the working cell from the non- working cell). In this regard, for example, performing a write operation on the right memory element (thus possible bit cell states (LL, LH _F ) followed by a positive bias read could separate the two types of cells but it requires an extra read operation. The write to both elements changes LH cell to HL cell to be combined with the HL cell in the other path, e.g., SA3=1. On the other hand, if read output SA3 is l 'bl (thus possible bit cell states: HL, OO, SS, HL _F , HpHp, L _F L _F , H _F H, L _F L), the process simply continues to the next step (i.e., without performing the write operation 1536). Subsequently, a read operation 1538 (e.g., corresponding to a third read operation as described hereinbefore) with a negative bias is performed to obtain a read output SA4. Then, at step 1540, it is determined whether the read output SA4 is at logic 0 or 1. If read output SA4 is l 'bO (thus possible bit cell states: OO, SS, HpHp, LpLp, HpH, LpL, HHp), the bit cell is determined to have a hard error. On the other hand, if read output SA4 is l'bl (thus possible bit cell states: HL and HLF), a write operation 1542 (e.g., corresponding to a third write operation as described hereinbefore) on both memory elements of the bit cell is performed (bit cell states: LH and LLp), followed by a read operation 1544 (e.g., corresponding to a fourth read operation as described hereinbefore) with a positive bias. For example, performing a write operation on the right memory element (thus possible bit cell states: HH, HLp) followed by a read operation with negative bias would differentiate the two types of cells, however it will incur an extra write cycle to recover HH cell. At step 1546, it is determined whether the read output SA5 is at logic 0 or 1. If read output SA5 is still l 'bl, the bit cell being tested is determined to have a hard error (thus possible bit cell state: LLp). On the other hand, if the read output SA5 is 1 'b0, the bit cell is determined to have a soft error and is recovered to the low state LH.

[0077] In various embodiments, the method/process described above with reference to FIG. 15A may be entirely sequential where only one sense amplifier and one write circuit is utilized. For example, read outputs SA1 to SA5 may be captured and stored after each read operation. It will be appreciated that the process can operate in parallel among different data path channels/route to increase the system level efficiency.

[0078] As can be observed from the flow diagram shown in FIG. 15A, there are two working cell paths, two soft error cell paths and four hard error cell paths. In this regard, Table 3 below tabulates the bit cell classification according to the paths as illustrated in the flow diagram of FIG. 15 A.

Paths Bit Cell Configurations

Wl HL

W2 LH

SE1 HH

SE2 LL

OH, OL, OS, OHp, OLp, HS, LS, H _F S,

HE1

LpS, HLp, HpLp, HpL

Table 3 - Bit ce c assi cation ase on t e i erent pat s in t e ow iagram of FIG.

15A

[0079] In various embodiments, the method/process described above with reference to FIG. 15A may be entirely sequential where only one sense amplifier and one write circuit is utilized. For example, read outputs SAl to SA5 may be captured and stored after each read operation. It will be appreciated that the process can operate in parallel among different data path channels/route to increase the system level efficiency.

[0080] FIG. 15B depicts a flow diagram 1550 of the differential mode error detection method by way of an example illustration only according to another example embodiment of the present invention. The flow diagram 1550 shown in FIG. 15B is the same as the flow diagram 1500 shown in FIG. 15A except for various differences in subsequent steps when the read outputs SAl and SA2 are different. In particular, if the read outputs SAl and SA2 are different, a write operation 1552 is performed on the second or right memory element in the bit cell (thus possible bit cell states: HL, LH, H _F L, LpH, OO, SS, HHp, LLp, HpHp, L _F L _F ). A negative biased read operation 1554 is then performed to obtain a read output SA3. At step 1556, it is determined whether the read output SA3 is at logic 1 or 0. If the read output SA3 is l'bl (thus possible bit cell states: HL, H _F L), a write operation 1558 is performed on both memory elements (thus possible bit cell states: LH, H _F H). On the other hand, if the read output SA3 is 1 'b0 (thus possible bit cell states: LpH, OO, SS, HH _F , LL _F , H _F H _F , L _F L _F ), the process simply continues to the next step (i.e., without performing the write operation 1558. Subsequently, a read operation 1560 with a positive bias is performed to obtain a read output SA4. Then, at step 1562, it is determined whether the read output SA4 is at logic 0 or 1. If the read output SA4 is l'bl (thus possible bit cell states: H _F H, OO, SS, HH _F , LL _F , H _F H _F , L _F L _F ), the bit cell being tested is determined to have a hard error. On the other hand, if the read output SA4 is l 'bO (LH, L _F H), another write operation 1564 is performed to both memory elements of the bit cell (thus possible bit cell states: HL, L _F L) and a negative biased read 1568 is subsequently performed. At step 1570, it is determined whether the read output SA5 is at logic 0 or 1. If the read output SA5 is 1 'b0, the bit cell being tested is determined to have a hard error (bit cell state: LpL). On the other hand, if the read output SA5 is I 'M, the bit cell is determined to have a soft error and is received to a high state HL. For example, the write operation to the second or right memory element may be realized modifying the configuration of the write driver that activates wtr to deliver a pulse to the second or right memory element while activating pdl to pull down the bit line connected to the first or left memory element.

[0081] FIG. 16 depicts a timing diagram of the differential mode error detection technique/method according to an example embodiment for illustration purpose only. As shown in FIG. 16, a 4-bit counter is used to control the timing of the input and output signals. When the signal ecen is asserted, a local reset signal rn will be generated to reset the counter outputs to 4'b0000 and the counter starts to count. There is a one-clock latency at the beginning of ecen assertion. All control signals are captured by registers and synchronized to the second counter output 4'b0010 before sent out to the read/write controller in order to eliminate/minimise glitches caused by the transition of counter output. As shown, the entire operation may take 15 clock cycles, including five read, three write and one error report operations and a synchronization clock. There are four biased read operations and the polarities of the biased reads depend on the nature of the ben signal. Three write operations, either to single or both elements, may be implemented in between read operations. An error signal may be reported at the last clock cycle should there be a hard error. The counter may be reset at the same time as the error signal which allows the next operation to start immediately after error report. When the signal ecen is de-asserted, all control signals goes to low. Accordingly, the total clock cycles for detection and recovery n addresses may be determined by \+\5n.

[0082] FIG. 17 depicts an example architecture 1700 of a differential mode TEF- RAM device based on 2T2R bit cell configuration having n+1 by m+1 memory array with i+1 data path channels according to an example embodiment. As shown, the differential mode TEF-RAM device is configured such that the ITIRs on the left of the bit cells in the same column are connected to the same bit line bll and source line sll and the ITIRs on the right of the bit cells are accessed by the same bit line blr and source sir. Each bit line may then be connected to the master bit line (mbl) through a column switch 1020 and a pull down transistor 1024. The left and right local bit lines that belong to the same data path channel are connected together to form the left and right master bit lines, respectively. The master bit lines are coupled to the sense amplifiers and read/write drivers and can thus be further accessed by the sense amplifiers and read/write drivers.

[0083] FIG. 18A depicts a schematic drawing of an error detection module 1800 for a TEF-RAM device according to various embodiments of the present invention. In particular, the error detection module 1800 is configured to control a read circuit and a write circuit of the TEF-RAM device to perform the method of error detection in the TEF-RAM device according to various embodiments of the present invention described herein to determine whether an error exists with one or more of a plurality of memory cells in the TEF-RAM device.

[0084] A computing system or a controller or a microcontroller or any other system providing a processing capability can be presented according to various embodiments in the present disclosure. Such a system can be taken to include a processor and a memory. For example, the error detection module 1800 may implemented in a computing system and/or coupled to a controller to receive various input signals, such as control signals as described hereinbefore (e.g., with reference to various timing diagrams as described herein) to perform the method of error detection in the TEF-RAM device and provide an output on whether an error exists with one or more of the plurality of memory cells in the TEF-RAM device. A memory used in the embodiments may be a volatile memory, for example a DRAM (Dynamic Random Access Memory) or a non-volatile memory, for example a PROM (Programmable Read Only Memory), an EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), or a flash memory, e.g., a floating gate memory, a charge trapping memory, an MRAM (Magnetoresistive Random Access Memory), a ReRAM (Resistive Random Access Memory) or a PCRAM (Phase Change Random Access Memory).

[0085] In various embodiments, a "circuit" may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a "circuit" may be a hard- wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A "circuit" may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions described herein may also be understood as a "circuit" in accordance with various alternative embodiments. Similarly, a "module" may be a portion of a system according to various embodiments in the present invention and may encompass a "circuit" as above, or may be understood to be any kind of a logic-implementing entity therefrom. For example, the error detection module 1800 may be implemented/realized as an error detection circuit configured to receive various input signals such as control signals as described hereinbefore (e.g., with reference to various timing diagrams described herein) to perform the method of error detection in the TER-RAM device and provide an output on whether an error exists with one or more of the plurality of memory cells in the TER-RAM device.

[0086] Some portions of the description have been explicitly or implicitly presented in terms of algorithms and functional or symbolic representations of operations on data within a computer memory. These algorithmic descriptions and functional or symbolic representations are the means used by those skilled in the data processing arts to convey most effectively the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities, such as electrical, magnetic or optical signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

[0087] Unless specifically stated otherwise, and as apparent from the following, it will be appreciated that throughout the present specification, discussions utilizing terms such as "scanning", "calculating", "determining", "replacing", "generating", "initializing", "outputting", or the like, refer to the action and processes of a computer system, or similar electronic device, that manipulates and transforms data represented as physical quantities within the computer system into other data similarly represented as physical quantities within the computer system or other information storage, transmission or display devices. [0088] The present specification also discloses a device or a module for performing/implementing the operations of the methods described herein, such as the error detection module 1800. Such a device/module may be specially constructed for the required purposes, or may comprise a general purpose computer or other device selectively activated or reconfigured by a computer program stored in the computer. The methods presented herein are not inherently related to any particular computer or other apparatus. Various general purpose machines may be used with programs in accordance with the teachings herein. Alternatively, the construction of more specialized device/module to perform the required method steps may be appropriate.

[0089] In addition, the present specification also implicitly discloses a computer program, in that it would be apparent to the person skilled in the art that the individual steps of the method described herein may be put into effect by computer code. The computer program is not intended to be limited to any particular programming language and implementation thereof. It will be appreciated that a variety of programming languages and coding thereof may be used to implement the teachings of the disclosure contained herein. Moreover, the computer program is not intended to be limited to any particular control flow. There are many other variants of the computer program, which can use different control flows without departing from the spirit or scope of the invention.

[0090] Furthermore, one or more of the steps of the computer program may be performed in parallel rather than sequentially. Such a computer program may be stored on any computer readable medium. The computer readable medium may include storage devices such as magnetic or optical disks, memory chips, or other storage devices suitable for interfacing with a general purpose computer. The computer program when loaded and executed on such a general-purpose computer effectively results in an apparatus that implements the steps of the method described herein.

[0091] The present invention may also be implemented as hardware modules such the various components/modules of the TEF-RAM device, including the error detection module 1800. More particular, in the hardware sense, a module is a functional hardware unit designed for use with other components or modules. For example, a module may be implemented using discrete electronic components, or it can form a portion of an entire electronic circuit such as an Application Specific Integrated Circuit (ASIC). Numerous other possibilities exist. Those skilled in the art will appreciate that the system can also be implemented as a combination of hardware and software modules.

[0092] FIG. 18B depicts a schematic drawing of a TEF-RAM device 1801 according to various embodiments of the present invention. The TEF-RAM device 1801 comprises a plurality of memory cells (or an array of TEF-RAM cells) 1802, a read circuit (or sense amplifier) 1804 coupled to the plurality of memory cells 1802 and configured to perform a read operation on any one of the plurality of memory cells 1802, a write circuit (or write driver) 1806 coupled to the plurality of memory cells 1802 and configured to perform a write operation on any one of the plurality of memory cells 1802, and an error detection module 1800 coupled to the read and write circuits 1804, 1806 and configured to control the read and write circuits 1804, 1806 (e.g., by way of control signal(s)) to perform the method of error detection in the TEF-RAM device according to various embodiments of the present invention described herein to determine whether an error exists with any one or more of the plurality of memory cells. For example and without limitations, the read and write circuits 1806 may be realized by any one of the read and write circuits described hereinbefore according to various embodiments of the present invention. The plurality of memory cells 1802 and the read and write circuits 1804, 1806 may also be configured or coupled together as described hereinbefore according to any one of the embodiments, such as, to realize a single mode TEF-RAM device or a differential mode TEF-RAM device. In various embodiments, the error detection module 1800 may receive one or more control signals 1812, such as to trigger the start of an error detection and/or recovery process/method, and generates an output 1812 when a memory cell being tested is determined to have an error (e.g., hard error).

[0093] For better understanding and as an example illustration FIG. 19 depicts a schematic block diagram of an example TEF-RAM device 1900 according to an example embodiment of the present invention. The TEF-RAM device 1900 comprises a plurality of memory cells (or an array of TEF-RAM cells) 1902, a read circuit (or sense amplifier) 1904 coupled to the plurality of memory cells 1902 and configured to perform a read operation on any one of the plurality of memory cells 1902, a write circuit (or write driver) 1906 coupled to the plurality of memory cells 1902 and configured to perform a write operation on any one of the plurality of memory cells 1902, a controller (or read/write controller) 1907 coupled to the read and write circuits 1904, 1906 and configured to control the read and write circuits 1904, 1906 by way of control signals to perform read and write operations, respectively, and an error detection module (or error detection and recovery controller) 1908 coupled to the controller 1907 and configured to control the controller 1907 controlling the read and write circuits 1904, 1906 to perform the method of error detection in the TEF-RAM device according to various embodiments described herein to determine whether an error exists with any one or more of the plurality of memory cells 1902. As shown in FIG. 19, the read/write controller 1907 may be configured to receive external input signals elk, address, rst, read, write, and din, and outputs wtl, wtr, pdl, and pdr to the write driver 1906, pre and sen to the sense amplifier 1904. For example and without limitation, the functionality of the read/write controller

1907 may be similar to the controller disclosed in Foong et al. In various embodiments, the read/write controller 1907 may comprise a number of D flip-flops to sample and breakdown the clock signal into phases according to the timing diagram shown in FIG. 12. The read/write controller 1907 may further comprise a decision making circuit to produce wt and pd commands based on the stored signal, and delay elements to align the output signals with clocks. The sense amplifier 1904 also receives the pre-charge voltage Vpre as input and outputs sa to read/write controller 1907 where it is captured and sent to the data path as dout. The error detection controller 1908 is at a higher hierarchy than the read/write controller 1907. In the example embodiment, the error detection controller

1908 receives common input signals elk, address and rst as the read/write controller and a unique ecen signal which indicate the period of error detection and/or recovery process. The error detection controller 1908 is configured to generate an error signal 1912, such as, to notify the system controller when a memory cell being tested is determined to have a hard error. In the example embodiment, the error detection controller 1908 is configured to send command/control signals rd, wsi, and wbo to the read/write controller 1907, nben,pben to the sense amplifier 1904 and receives sense amplifier output sa and a strobe signal stb to capture the five SA outputs into registers for processing, including whether the memory cell being tested has an error. In various embodiments, the error detection controller 1908 may comprise a counter (e.g., 3-bit for single mode TEF-RAM and 4-bit for differential mode TEF-RAM) which tracks the clock number when ecen is asserted, and various logic circuits configured to decide when to perform read or write operation to the memory cell specified by the address signal (addr) (e.g., as illustrated in various timing diagrams disclosed herein). The stb signal is synchronized with read operation that captures the serial sa signal towards the end of each read operation to capture the sense amplifier output. The sense amplifier output may then be judged by simple logic circuit to determine the path to be taken down the flow diagram of, e.g., the single mode error detection method as illustrated in FIG. 8 or the differential mode error detection method as illustrated in FIG. 15A or 15B.

[0094] For illustration purpose and to demonstrate the error detection techniques/methods described according to various embodiments of the present invention, simulation results of the single mode and differential mode error detection techniques/methods will now be presented with reference to FIGs. 20A, 20B and 21A to 21C. In the simulations, the memory cell is modeled with Verilog-A and its high and low resistances are at 250K ohms and 100K ohms, open and short cells are represented by fixed resistors of 1M ohms and 100 ohms, and unswitchable cells at high and low resistance are represented by resistors of 250K ohms and 100K ohms, respectively.

[0095] FIG. 20A shows the simulation results of the single mode error detection technique for two example cases of working/functioning cell at high (H) and low (L) resistance states, respectively. From FIG. 20A, it can be observed that the two example cases went through the mid-branch path of the flow diagram in FIG. 8 and two read and two write operations were performed. At the end of the detection process, the memory cell being tested was reverted to its original resistance state and no error signal was generated/activated in either case.

[0096] FIG. 20B shows the simulation results of the single mode error detection technique for four example cases of hard error cells. From FIG. 20B, it can be observed that hard error cells Hp and O went through the same left branch path of the flow diagram in FIG. 8 where the two SA outputs (SA1, SA2) are l 'bl and only one write operation was performed. Hard error cells Lp and S shared the same right branch path of the flow diagram in FIG. 8 where the two SA outputs (SA1, SA2) are 1 'b0. It can also be observed that the error signal was generated/activated at the end of the detection cycle for all four cases. [0097] FIGS. 21 A to 2 ID show the simulation results of the differential error detection technique according the flow diagram described in FIG. 15A. The simulation results for the two example cases of working cell are shown in FIG. 21 A. It can be observed that three read operations were performed and the SA outputs (SA1, SA2, SA3) are I 'M, I'M and l 'bO, and l'bO, l 'bO, and l'bl for HL and LH cases, respectively. Two write operations to both memory elements of the memory cell being tested were performed which maintained the original states of the bit cell as shown by the transition of the two elements' resistances rtef and rtef r. It can also be observed that no error was reported at the end of the detection process.

[0098] FIG. 2 IB shows the simulation results for two example cases of soft error cells. It can be observed that the detection process went through the entire flow chart in FIG. 15 A with five read operations. Three and two write operations were performed for each of the cases of HH and LL. The final resistance states for the two cases show that soft errors were recovered to the default LH state. It can also be observed that no error was reported at the end of the detection process since the soft error was recovered.

[0099] FIG. 21C shows the simulation results of two example cases of unswitchable cells LLF and HHF. It can be observed that the case of LLp went through two write operations and all five read operations before error was reported. This case went through the path leading to HE4 in the flow chart shown in FIG. 15A and HHpwent through the path leading to HE3 in the flow chart. It can also be observed that errors were reported at the end of both detection processes.

[00100] FIG. 2 ID shows the simulation results for four example cases of hard error cells, involving open and short hard error cases. It can be observed that the cases of hard errors OH and SL went through the path of the flow diagram leading to HE1 and HE2 in FIG. 15A, respectively. The cases of hard errors OO and SS went through the path of the flow diagram leading to HE4 in FIG 15A. It can also be observed that errors were reported at the end of the detection process for all four cases.

[00101] FIG. 22A depicts a flow diagram of an error detection process/method 2200 for a single mode TEF-RAM device using mid-point reference cell based sensing scheme/method according to various embodiments of the present invention. As a first step 2202, a check may be performed to determine whether the TEF-RAM device is in error detection mode as controlled by the signal ecen. If the signal ecen is low, the TEF- RAM device may go into normal operation mode (i.e., single mode normal read and write operation) 2204. On the other hand, if the signal ecen is high, the memory enters error detection mode whereby a differential mode error detection technique is applied in step 2206 on the mid-point reference cells to identify/detect hard error cells. For example, the error information could be used by system controller to allocate resources to replace or mask the faulty cells. After the completion of the error detection process on the mid-point reference cells, a single mode error detection technique may be applied in step 2208 to identify/detect hard error in main memory cells. Similarly, the information could be utilized at system level to improve the yield of the TEF-RAM device.

[00102] FIG. 22B depicts a flow diagram of an error detection process/method 2220 for a single mode TEF-RAM device using mid-point voltage or current based sensing scheme/method according to various embodiments of the present invention. In such a sensing scheme, reference voltage or current for sensing is directly supplied internally or externally. As a first step 2222, a check may be performed to determine whether the TEF- RAM device is in error detection mode as controlled by the signal ecen. If the signal ecen is low, the TEF-RAM device may go into normal operation mode (i.e., single mode normal read and write operation) 2224. On the other hand, if the signal ecen is high, the memory enters error detection mode whereby a single mode error detection technique is applied in step 2228 to identify/detect hard error cells. In this regard, the single mode error detection technique is directly used to identify/detect the hard error cells in the main memory array.

[00103] FIG. 22C depicts a flow diagram of an error detection process for the differential mode TEF-RAM device according to various embodiments of the present invention. As a first step 2242, a check on the mode of operation of the TEF-RAM device may be performed. If the TER-RAM device is in an initialization mode prior to product testing and shipping, a differential error detection technique may then be activated/used in step 2244 to identify hard error cells and recover soft error cells. On the other hand, if the TEF-RAM device is in a normal operation mode, bias may be disabled in the biased sense amplifier, and both write pulses may be generated by the write controller to perform normal differential read and write operations in step 2246. However, if at step 2248 it is determined that the TEF-RAM device is in error detection mode in the field of operation, the differential mode error detection technique may be applied at step 2244 to the main memory cells of the differential mode TEF-RAM device. The error information may then be utilized at system level to improve the yield of the TEF-RAM device prior chip shipping and in the field of operation.

[00104] It will be appreciated to a person skilled in the art that the terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[00105] While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.