METHOD FOR EVALUATING IMPURITY GETTERING ABILITY OF EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER

Title:

METHOD FOR EVALUATING IMPURITY GETTERING ABILITY OF EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER

Document Type and Number:

WIPO Patent Application WO/2018/159140

Kind Code:

A1

Abstract:

The present invention provides a method for evaluating the impurity gettering ability of an epitaxial silicon wafer, the method being capable of evaluating with high accuracy, the gettering behavior of impurities in a carbon-dissolved modified layer formed immediately below an epitaxial layer. This method is characterized in that a carbon-dissolved modified layer formed immediately below an epitaxial layer is analyzed by a three-dimensional atom probe method and the impurity gettering ability in the modified layer is evaluated on the basis of a three-dimensional map of carbon in the modified layer, the three-dimensional map being obtained by the analysis.

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Inventors:

SHIGEMATSU SATOSHI (JP)
OKUYAMA RYOSUKE (JP)
KURITA KAZUNARI (JP)

Application Number:

PCT/JP2018/001471

Publication Date:

September 07, 2018

Filing Date:

January 12, 2018

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Assignee:

SUMCO CORP (JP)

International Classes:

H01L21/322; H01L21/20; H01L21/265; H01L21/66

Foreign References:

JP2006029786A	2006-02-02
JP2012159415A	2012-08-23
JP2014099478A	2014-05-29
JP2015130397A	2015-07-16

Attorney, Agent or Firm:

SUGIMURA, Kenji (JP)

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