Title:
METHOD FOR EVALUATING SILICON WAFER
Document Type and Number:
WIPO Patent Application WO/2019/130633
Kind Code:
A1
Abstract:
Provided is a method for evaluating a silicon wafer by which it is possible to carry out a non-destructive and non-contact inspection for a slip that exerts an influence on the electrical properties of a semiconductor device while causing as few restrictions as possible on the surface state of the silicon wafer and the processing details thereof. This method for evaluating a silicon wafer comprises: a section analysis step in which a heat-treated single crystal silicon wafer is partitioned into equally spaced sections of between 1 mm2 and 25 mm2 inclusive, and the presence or absence of distortion in each of the sections is determined on the basis of a depolarization value of infrared polarization; and a screening step in which sections that were determined in the section analysis step as having distortion and that do not have a number of adjacent sections exceeding a prescribed threshold are evaluated as being of a good quality.
Inventors:
SUDO HARUO (JP)
ARAKI NOBUE (JP)
OKABE KAZUKI (JP)
ARAKI KOJI (JP)
ARAKI NOBUE (JP)
OKABE KAZUKI (JP)
ARAKI KOJI (JP)
Application Number:
PCT/JP2018/027425
Publication Date:
July 04, 2019
Filing Date:
July 23, 2018
Export Citation:
Assignee:
GLOBALWAFERS JAPAN CO LTD (JP)
International Classes:
H01L21/66; G01N21/88; G01N21/956
Domestic Patent References:
| WO2009102051A1 | 2009-08-20 |
Foreign References:
| JP2015073049A | 2015-04-16 | |||
| JP2005292054A | 2005-10-20 |
Attorney, Agent or Firm:
KINOSHITA Shigeru (JP)
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